Issue



Effects on Packaging from the Progression of Wafer Technologies


07/01/2005







onsumer electronics today are demanding higher performance devices, smaller form factors, and lower power consumption.It is becoming very difficult to achieve these demands with conventional silicon-based CMOS architecture. Over the years, optical lithography has consistently pushed the processing limits as the industry drove down the 180-, 130-, and 90-nm silicon process nodes. Ninety-nanometer is starting to roll out at more fabs today, along with the challenges of deep sub-wavelength lithography, silicon-on-insulator, strained silicon, copper metal, low-k dielectric, as well as replacing the aggressive conventional “cleans” that remove particles by etching. These “fab challenges” can no longer be independent from packaging.

The interdependency between wafer technology and packaging has never been greater. I have seen more package qualification failures attributed to device interaction in the last 2 years than I did in the previous 20 years! Historically, the industry was able to qualify a new packaging technology for all silicon nodes. Today, however, we can see a specific silicon node from a specific fab that requires a different or custom packaging process.

Device speed has historically been dominated by effects at the transistor level, rather than by interconnects. But this run came to an end when the interconnect delay became a significant contributor to the overall circuit speed. Switching to copper wiring, with lower electrical resistance than aluminum, provides a significant boost to interconnect performance. To further boost performance, the traditional interconnect insulator of SiO2 is being replaced by a progression of low-k dielectric materials yielding lower capacitance. The copper and dielectric materials are layered in a complex stack with an increasing number of layers.

Package materials and processes have been developed to reduce stresses that might cause the brittle low-k dielectric to fracture when stressed in a package. Most packaging factories are assembling many devices with low-k today. But variations in fab locations, materials, and processes, plus the design of stacked copper metal and dielectric, can affect the reliability and manufacturability of a packaged device. The packaging factory is continuously testing out the newest wafer technologies to confirm if they can be built without problems.

The copper wire bond pads on the device, combined with many other variables (barrier metals, aluminum cap, pad pitch, mold compounds, wirebond process, wire type, etc.), will have the ability to potentially create long-term reliability issues on the gold wire bonds called “intermetallics.” This reliability failure depends on the device pads, and cannot be completely controlled by the packaging processes. Wafer technology and its variables on the copper metal pads, such as the barrier metals (TaN, TiN, TiW, etc.) and the aluminum cap, will have a significant effect on the packaged devices. Together, the fab and packaging factories have learned much in the last 2 years. However, each new silicon node must continuously be tested to determine if it falls into the existing process windows for packaging, or if it requires new package process variations.

Thinner packages and 3-D or stacked devices in a package have pushed some silicon devices down into the 50- to 100-µm thickness range. Packaging factories had to develop effective handling technologies and stress relief processes to cope with the potential of device cracking. The thinning process and resulting stress in a packaged state can impact the device performance of certain silicon technologies. More interactions!

Wirebonding over active circuits allows the device size to shrink. The reliability of this packaged device (and the process window) depends on the metal and dielectric stack-up out of the fab. Successful flip chip products are a trade-off between the device design and the package design to optimize size, cost, and performance. Device design and fabrication must be done with an understanding of its effects on packaging.

Packaging and silicon technologies are coupled more closely with each future generation of silicon. The packaging world will find many surprises and interdependencies as the silicon nodes march down from 90 nm to 65 nm and 45 nm. MEMS device technology today and nanotechnology in the future will further extend these interdependencies. Fab and packaging groups must work closely together to successfully allow future semiconductor products to shrink and perform faster. Moreover, packaging companies must be included as a full-time partner to help drive the advances in today’s device technology.

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MICHAEL J. STEIDL, VP of Advanced Packaging, may be contacted at Amkor Technology, 1900 S. Price Road, Chandler, AZ 85248; 480/821-2408; e-mail: mstei@amkor.com.