Wire Bond Vs. Flip Chip Packaging
A TECHNICAL TRADE-OFF ANALYSIS
BY GREGORY PHIPPS
In the world of high-speed/high-performance package design, the primary packaging solution is flip chip in package (FCiP) technology. It is widely understood that flip chips offer a variety of benefits compared to traditional wire-bond packaging, including superior thermal and electrical performance, the highest I/O capability, substrate flexibility for varying performance requirements, well-established process equipment expertise, proven construction, and reduced form factors. Despite these benefits, flip chips have not been a cost-effective packaging solution.
The costs associated with flip chips stem from wafer fabrication vendors, substrate vendors, and assembly/packaging subcontractors. The increased costs are realized at every step of the process from repassivation and redistribution (RDL) at wafer fabrication, to the high-performance multilayer organic build-up substrates provided by the substrate vendor. With the added costs of assembly, the flip chip package becomes a cost-prohibitive option.
Recently, packaging and assembly houses have taken great steps toward providing cost-effective solutions by offering flip chip packaging options on a standard leadframe (FCSOL), quad flat pack no leads (QFN), and standard bis-maleimide triazine (BT) resin substrates. While there may still be costs upfront in the wafer fabrication process, assembly houses are using proven technologies and innovative processes to provide customers with better solutions.
It is the cost-effective, proven technologies and innovative processes that continue to interest customers and drive designers to maximize package performance. Designers must understand key electrical and thermal performance package challenges, and work to minimize the negative impacts. By maximizing the strengths of the technology, using standard package material sets, robust manufacturing, and assembly processes, the die-up, wire-bonded, plastic overmolded, BT laminate package technology is a viable solution for high-speed design applications.
To understand substrate performance requirements, it is important to know the specific performance requirements and capabilities of the substrate and assembly technology. Many of today’s electronic devices are operating at high frequencies, and signal integrity is an important consideration. The general line of thinking is that by eliminating the wire bonds, which can act as a bottleneck in the package, flip chips offer improved electrical performance. While this is true, a number of design techniques can be used that allow a standard wire bond technology to achieve the performance requirements demanded by GHz clock speeds (Figure 1). Also important, are:
Figure 1. A number of design techniques can be used that allow a standard wire bond technology to achieve performance requirements demanded by GHZ clock speeds.
Identifying Critical Signals. In many cases, critical signals will be identified as a differential pair or single-ended signal with a specific clock speed and have signal impedance requirements. For differential pairs, the complementing signals must be routed parallel to each other with the same length or skew to take advantage of the coupling, noise rejection, and differential impedance characteristics that are created from this pairing. Single-ended signals also have an impedance and requirement in relationship to other single-ended signals.
The substrate technology and layer stackup are a key element in achieving the signal impedance requirement. As with flip chip substrates, wire bond laminate substrates are flexible enough to accommodate reference plane layers to achieve impedance requirements. Microstrip also can be accomplished on flip chips, but is more common in wire bond situations where the substrate has 4 layers. The microstrip structure is composed of a transmission line configuration consisting of a conductor over a parallel reference plane (voltage or ground), separated by dielectric material. Benefits of this approach include controlled signal impedance, reduced signal crosstalk, and reduced signal inductance. Based on this construction, trace widths and spacing can be determined to achieve the correct differential or single-ended impedance requirement.
Die Pad Ring Design and Placement. As the wire density per die quadrant increases, the wire lengths and angles increase. The die pads in the center of each quadrant will have wires with minimal angles and the potential to have the shortest length. If the high-speed signals can be located in the center pads of the quadrant, wire lengths less than 1.0 mm can easily be achieved.
In addition to the location of the high-speed signals on the die pad ring, the consideration of adjacent signals is also important. To prevent crosstalk and eliminate the potential of simultaneous switching noise (SSN), it is advantageous to surround the single-ended or differential pair high-speed signals with a reference ground signal.
The ability to have ground wires adjacent to high-speed signals creates a 3-D shielding effect and provides the opportunity to continue the groundshield via traces on the substrate. Continuing from the ground bond fingers, traces can be routed alongside the high-speed signals and shielded from the noise and crosstalk potential of adjacent signals.
Wire Bond Diameter. Through the characterization and measurement of inductance, it is understood that the larger the wire diameter, the lower the inductance value. To be safe, the standard request has been to maximize the wire diameter for improved performance. Increasing the wire diameter might have little effect on performance as speed climbs into the GHz range, due to what is known as the “skin effect,” occuring at high frequencies where current travels on the outer layers of the conductor and does not use the entire conductor for signal transmission.
Substrate Signal Path Connectivity. Minimizing the critical signal path lengths by considering the ball locations with respect to the die pad/bond finger location will benefit electrical performance. Actual ball locations depend upon die size, bond finger density, and finger location. If the critical signals are given priority when considering die and package design, the wire bond length will be minimized and the routed signal paths will straight and short.
Substrate Plating Requirements. If the substrate technology uses an electrolytic plating process, every signal will have a plating trace for the Ni/Au deposition process. For critical signals with high clock speeds, long plating traces will have a negative effect, causing signal reflection and the potential for an impedance mismatch.
Depending upon the die size and finger locations, one alternative is to allocate high-speed signals to outside package ball locations, minimizing plating trace lengths. If the optimal ball locations are on the inside ball locations, plating can be accomplished by using a semi-additive plating process that requires no plating traces, or an etch-back plating process can be used to reduce long plating traces that extend to the package edge to small stubs.
There are design techniques that allow a standard wire bond technology to achieve the performance requirements demanded by clock speeds in the GHz range. Working closely with package characterization data helps guide and determine the necessary design techniques to meet performance requirements.
From thermal performance criteria, higher-frequency devices tend to reach higher temperatures. The need for low thermal conductivity can push a device into a larger package size, creating longer signal paths that could adversely effect signal performance. Understanding that form factor and thermal performance are both critical, there are a number of options to consider that can help achieve the required thermal performance without sacrificing the package size.
Thermal Ball Matrix. On ball grid array (BGA) packages, adding a thermal ball matrix under the die provides a direct thermal dissipation transfer path from the package to the PCB.
Increase Substrate Layer Count. Increasing the layer count (i.e. from 2 to 4 layers) adds additional copper to the package and serves to improve thermal performance. Typically, a 4-layer substrate is a minimum because of the signal impedance requirement.
Figure 2. Effect of Cu substrate thickness on thermal performance.
Maximize Via Count on Die Attach Pad (DAP). This improves thermal dissipation from the backside die surface to the internal planes and thermal solder balls. Figure 2 shows improvement in thermal performance as the number of vias increase.
Copper Plane Thickness. Increasing copper thickness (i.e. 35 µm to 70 µm) of the power and ground planes on a multilayer substrate improves thermal performance. Figure 3 shows the decline in the theta-ja values as the Cu thickness increases.
Figure 3. Effect of thermal via on thermal performance.
Heatsink or Slugs. Use of an internally embedded slug or externally attached heatsink provides additional increases.
Filled Vias. As well as other improvements, plugging via drill holes with thermally conductive epoxy provides improvements.
Even though standard wire bond packages do not typically use the integrated heatsink solution or option to leave the backside of the die exposed to air as seen in flip chip package options, there are many options that will improve thermal package performance and continue to promote wire bond technology as a viable package solution for high-speed applications.
In the future, the material sets, substrate construction, and process will continue to evolve. Vendors will continue to improve substrate technology, routing densities, layer structure, and other factors - all of which affect performance. Using the criteria of electrical performance, thermal performance, substrate connectivity, and package assembly considerations can provide a high-speed solution in a wire bond package.
These technical improvements enhance the continued acceptance of wire bond packaging, while customers will continue to require cost-effective packaging solutions that do not sacrifice performance. It is clear that standard wire bond technology is still a choice solution for many wireless, networking, and communications applications in which performance and compactness are critical considerations.
Huili Fu and Kin Ming Leung, “Thermal Enhancement of Fine Pitch Ball Grid Array Package by Substrate Design,” Advanced Interconnect Technologies Ltd., Internal Study 2003.
GREGORY PHIPPS, design manager, may be contacted at Advanced Interconnect Technologies Inc., 1284 Forgewood Ave., Sunnyvale, CA 94089; 408/734-3222; e-mail: email@example.com.