Through-wafer Via Etching
The technical challenges and the manufacturing complexity confronting conventional methods of increasing IC device density in 2-D are increasing at a high rate. In 1965, Moore’s Law postulated that the number of transistors per chip would double roughly every 2 years, and for a considerable period of time this has held approximately true. However, improvements in transistor performance and possibilities for increased device density brought about by fundamental changes in the device materials systems such as strained silicon, SiGe, or by the introduction of diminishing device dimensions carry a high development cost and require considerable time for their qualification. Furthermore, they require extensive capital equipment investments to enable high-volume manufacturing, and it is difficult to implement device geometry reductions at a rate consistent with the original prediction of Moore’s Law.
The resultant slower rate of device area shrinks and the rate at which the number of transistors per die can be increased while maintaining reasonable manufacturing yield is unlikely to be maintained at a high enough rate to satisfy the historical prediction. Consequently, the interval between the introduction of future device generations is expected to be extended. Chips with a higher device density and increased integration require a larger number of I/O leads. This leads to smaller I/O pad pitch on the device periphery and increased packaging challenges, unless the connections can be redistributed over the chip area. An emerging alternative to 2-D increases in device density per unit area is to extend devices to 3-D. In the absence of genuine 3-D electronic device architectures, this is most readily achieved by chip stacking. Currently, stacked devices are interconnected by wire bonding, which is a complex process.
In parallel with the demand for increased device density within a chip, there is a desire for increased overall circuit functionality. This is seen in applications such as highly integrated microelectromechanical systems (MEMS) and integrated RF modules, where mechanical or sensing functions may be integrated with digital and analog electronics, optical components, passives, wireless circuits, etc. System-on-chip (SoC) or system-in-package (SiP) concepts provide means of realizing these integrated systems, but once again, 3-D integration by stacking of dedicated individual chips offers an alternative.
Silicon Deep Reactive Ion Etching
Given the challenges facing wire bonding of stacked chip modules, through-wafer via formation is a key process technology required for improved implementation of 3-D chip stacking. When through-wafer vias are micromachined by dry etching, and subsequently filled with metal, they can be used as chip-to-chip interconnection paths occupying a minimum amount of chip surface “real estate.”
Through-wafer plasma etching processes are widely used in mass production of chip scale packages (CSPs) for CMOS image sensors. In these cases, however, the etching process is used to etch scribe-channels (“streets”) with a tapered sidewall between the individual die, an application fundamentally different from the requirement for deep, small diameter via holes etched through a silicon device. For 3-D chip stacking processes, the ideal silicon etching process is anisotropic (highly directional) and capable of etching close to vertical holes with a high aspect ratio. In MEMS device manufacturing, anisotropic deep reactive ion etching of silicon is a mature process technology that is used for creating 3-D mechanical structures in silicon-based MEMS devices. Many mass-produced MEMS components now feature plasma-etched structures, and many of these same process concepts can be directly applied to through-wafer etching for advanced packaging.
Deep reactive etching of silicon, frequently described as silicon micromachining, is a pattern transfer technique widely used to manufacture Si-based MEMS and power electronic devices. This method provides highly directional (almost completely anisotropic) etching, ensuring that the etch mask on the wafer surface is faithfully replicated in the underlying silicon. In MEMS manufacturing, deep reactive etching processes are widely used to pattern both thick polycrystalline silicon films and bulk single-crystal wafers. Due to the selectivity of the process between silicon and a wide range of other materials, it is compatible with conventional photoresist and dielectric hard masks.
Given the high level of interest in packaging of MEMS devices, SiP, and 3-D IC stacks, numerous intensive development projects are in progress, and silicon micromachining processes play a pivotal role in a number of advanced die packaging processes. The range of silicon etching processes under investigation covers a wide spectrum, including uniform silicon wafer thinning, controlled etching of scribe channels and vias, with precisely controlled sidewall slope and base width, and micromachining of high aspect ratio though-wafer vias.
Silicon deep reactive etch processes are most frequently applied in high-density, inductively coupled plasma (ICP) etching systems, typically using the time-multiplexed etching concept patented by Robert Bosch GmbH of Germany.1 The concept and industrial implementation have been described elsewhere in detail.2-5 In summary, however, the process comprises a sequence of alternating process steps of silicon etching and protective polymer deposition, each of a few seconds duration in a high-density plasma. Each etching step provides a short period of high rate somewhat isotropic (non-directional) silicon removal. Conversely, each polymer deposition step generates a passivating polymer film that prevents lateral etching of the exposed silicon sidewalls during subsequent etching cycles. By applying this series of alternating etching and deposition steps, the silicon micro-machining process proceeds as a series of “bites” into the silicon, each on the order of 0.5 to 5.0 µm deep, depending on the actual etch cycle time.
Figure 1. Typical examples of a Si structure micromachined with Si deep reactive ion etching processes, incorporating both narrow and wide hole and trench structures.
Since this micromachining process is typically anisotropic, it is a suitable technique for creating vertical, high aspect ratio holes and trenches in silicon. In MEMS applications, silicon micromachining processes are used to fabricate a variety of mechanical structures. Frequently, however, micromachined trenches and cyclindrical holes with high aspect ratio are required - typical examples of micromachined structures incorporating both narrow and wide features are shown in the SEMs in Figure 1. Structures of this type can be used to form interconnecting through-wafer vias in stacked chip and SiP applications.
Micromachining Process Tools
The original time-multiplexed etching process comprises a series of sequential plasma etching and deposition cycles, each a few seconds in duration, which over the duration of the process generate an approximately vertical etched silicon sidewall.
The basic tool used in the Bosch-type process is an inductively coupled plasma (ICP) etching system. These systems are characterized by their capability to generate high-density plasmas in which the RF energy is coupled into process gas flowing through the process chamber by an external antenna. An independently controlled second RF subsystem can be used to apply a DC bias voltage to the substrate, independently of the RF power applied to the plasma. Depending on the choice of process gas flowing through the system, the plasma will contain high densities of electrons, positive ions, and highly reactive chemicals (such as F atoms). In silicon deep reactive etch processes, SF6 gas typically is used as the etching process gas during each etching step. The resultant F atoms in the plasma are particularly important, because they are the primary etchant species for the silicon. In this case, the etching process occurs by spontaneous reaction of the F atoms with the exposed silicon surface. By definition, however, the resulting etching process is isotropic.
In contrast, a plasma in a fluorocarbon gas such as C4F8 produces a high density of chemically reactive polymer precursor species. During each polymer deposition step, a thin polymer film is deposited isotropically over the entire wafer surface. In the succeeding SF6 etching step, the positive ions in the plasma are used to sputter etch the polymer film selectively from the base of the silicon structure, permitting the F atoms to react spontaneously with the exposed silicon. While the etching reaction is predominantly chemical and isotropic, the process step time is short and the extent of any lateral etching is restricted to less than the vertical depth of a single etching step. The thin polymer film deposited during the deposition steps prevents lateral etching of the silicon sidewalls during any succeeding etching step. The resulting “ripple” (or “scallops”) created in the etched silicon sidewall as a result of the alternating etching and deposition cycles is a characteristic of the Bosch-type process. The end result is a vertically etched silicon structure with a characteristic texture in the sidewalls, formed by the “scallops.”
Figure 2. On the left, “scallops” are shown in the sidewall of a trench etched into Si with a Bosch-type process. On the right, the Si deep reactive ion etching process was optimized to minimize the sidewall scallops.
In some applications, the process conditions are adjusted to minimize the size of the “scallops” to provide mirror surfaces in silicon-based optical switches. Scanning electron micrographs (SEMs) of cross sections of some typical trenches etched with this approach are shown in Figure 2. These SEMs illustrate the range of sidewall conditions that can be achieved by adjustment of the process conditions.
Etch Rate & Depth
The Bosch-type process depends on chemical reactions, and the average etch rate of the silicon surface is controlled by two factors: the rate at which reactive species generated by the plasma can diffuse to the etch front; and the rate at which etch byproducts created by the reaction of the etchant species with the silicon can diffuse away from the surface.
Figure 3. The dependence of Si etch rate on etch depth in high aspect ratio vias.
During the etching of via holes with high aspect ratio (etched depth to via diameter), the rates of diffusion to and from the silicon surface are reduced relative to shallow etched structures. This reduces the silicon etch rate, as the depth of the structure increases. An example of this effect is shown in Figure 3.
Figure 4. The top image shows a 20-µm-diameter via etched at about 3.5 µm/min. Note the absence of scallops. The lower image shows 20-µm-diameter via etched at about 3.5 µm, with scallops.
Etch rate enhancement strategies in silicon deep reactive etch processes typically result in an increase in the amount of silicon etched during each etch step. This effect can be observed as an increase in the size of the characteristic “scallops” seen in the etched sidewall. Two examples are shown in Figure 4. The cross-sectional SEM (top) shows a via etched at ~3.5 µm/min., while the lower image shows a SEM of a similar via etched at ~10.9 µm/min.
Figure 5. The image on the left is an example of “etch-stop” in a trench, etched with a non-optimized procecss. Optimization of a Si deep reactive ion etch process to avoid “etch-stop” is shown on the right.
The dependence of etch rate on depth has two important outcomes:
- Process parameters that are optimum at the beginning of the etching process, when the structure has a low aspect ratio, are not optimized for later stages of an etching process when the high aspect ratio is higher. To counter this phenomenon, one company* developed the “parameter ramping” concept.6,7 This technique enables key process parameters to be continually adjusted during high aspect ratio etching processes. This ensures that the instantaneous process conditions are matched to the actual aspect ratio at any given point in the process. As an example, it may be chosen to reduce the process pressure to ensure that etchant species and byproducts can diffuse readily into and out of the deepening structures. This avoids the phenomenon of “etch stop,” a problem that arises when the rate of polymer deposition exceeds the rate of polymer removal in the base of high aspect ratio structures - causing the process to “stall” at some specific depth. Simultaneously, to compensate for the reduction in average etching rate that follows from the reducing process pressure, the duration of the etching step may be increased continuously during the process. Figure 5 (above) shows an example of the etch stop phenomenon, while the image on the right shows the result obtained when parameter ramping is applied to the etching process.
- Since the average etching rate decreases dramatically with via depth, better overall productivity may be obtained for a via process by etching consecutively from each side of the wafer. This approach requires two patterning steps and a photolithography system featuring double-sided wafer alignment, but the time saved as a result of the higher average rate in the etching process may compensate for the additional photolithography steps. As an example, using the data for the 20-µm-diameter vias previously discussed, a 200-µm-deep via is etched in about 39% of the time required to etch a 400-µm via. Roughly, the same ratio applies to the 30-µm-diameter vias. A considerable etch time saving can be realized by etching from each side of the wafer. Clearly, this becomes effective when the cost of the additional photolithography requirements is less than the cost of the extended etching process. In Figure 6, an example of this approach shows a cross section of a 20-µm-diameter through-wafer via achieved by etching sequentially from each side of the wafer.
Silicon micromachining processes are becoming widely adopted in advanced device packaging applications, including through-wafer via etching for 3-D chip stacking concepts. In cases where vertical through-wafer vias are needed, processes comprising advanced variants of the Bosch-type time-multiplexed process have been shown to provide suitable results. Optimized etching processes are anisotropic, with undercut limited to a fraction of a micrometer per mask edge in the best cases, while the size of the characteristic “scallops” in the sidewall is limited to a few tens of nanometers by using an appropriate hardware configuration. The etched vias can be readily filled with metal, providing a viable interconnection technique for stacked ICs or ICs on silicon interposers.
*Surface Technology Systems Plc.
- F. Laermer, A. Schilp - Patent No. DE 4241045 (US 5501893), 1994.
- A.A. Chambers , “Applications for Silicon Micromachining in Advanced Device Packaging Schemes,” Proceedings of the SMTA International Wafer-Level Packaging Congress (IWLPC, San Jose 2004).
- J.K. Bhardwaj, H. Ashraf, “Advanced Silicon Etching Using High-density Plasmas,” Proceedings of Micromachining and Microfabrication Process Technology Symposium of the International Society for Optical Engineering, Austin, Texas, October 23-24 1995.
- J. Bhardwaj, H. Ashraf, A. McQuarrie, “Dry Silicon Etching for MEMS,” Presented at the Symposium on Microstructures and Microfabricated Systems at the Annual Meeting of the Electrochemical Society, Montreal, Quebec, Canada. May 4-9, 1997.
- H. Ashraf, J. K. Bhardwaj, S. Hall, E. Guibarra, J. Hopkins, A. M. Hynes, I. Johnston, L. Lea, S. McCauley, G. Nicholls, P. O’Brien, “Defining Conditions for the Etching of Silicon in an Inductive Coupled Plasma Reactor,” Proceedings of the Materials Research Society Fall Meeting, Boston, MA, USA, November 29-December 3, 1999.
- J. Hopkins, H. Ashraf, J. K. Bhardwaj, A. M. Hynes, I. Johnston, J. N. Shepherd, ”The Benefits of Process Parameter Ramping During the Etching of High Aspect Ratio Silicon Structures, ”Proceedings of the Materials Research Society Fall Meeting, Boston, MA, USA. December 1998.
- D.M. Haynes, B. Khamsehpour, H. Ashraf, J. Hopkins, J.K. Bhardwaj, A.M. Hynes, M.E. Ryan - Patent No. US 6051503, 2000.
ANDREW A. CHAMBERS, technology director, HUMA ASHRAF, process manager, JANET HOPKINS, R&D process engineer, and JEFFREY R. PINK, senior process engineer, may be contacted at Surface Technology Systems Plc., Imperial Park, Newport, NP10 8UJ, U.K.; 44 1633 652400.