What Is IC/Package Co-design?


Enabling Global Optimization & Characterization of Design

Co-design is the unification of the model of the entire design’s fabrics (IC, package, and board) into a common design environment that allows global optimization and characterization of the design under development.

We often hear the term “system interconnects” used to refer to buffer-to-buffer connections across the entire design fabric. Co-design represents the process for managing and optimizing system interconnects.

Successful co-design requires the following: convergent design methodology, closed-loop ECO processes, and full sign off to support concurrent manufacturing of all fabrics.

The concept of co-design drives the need to integrate existing EDA vertical tool environments into a single solution. Co-design encompasses a complex design chain of system, SoC, custom circuit, package, and board designers. Design trade-off complexities between the various fabrics and design chain entities must be captured, distributed, and managed using a shared co-design model.

Co-design Environment

The co-design environment consists of three key elements:

  • Design data representing the various design technologies, the rules, and reusable IP within those technologies;
  • A team of engineers organized to develop and integrate each of the design’s key components;
  • A tool-enabled design process that minimizes design risk and provides continuous convergence on the solution.

Co-design Data

The co-design environment is supported by a rich set of data such as component libraries, manufacturing technologies, reusable design concepts, models, and other necessary items (Figure 1). The content and format of each entity in the library is well defined and populated.

Figure 1. The co-design environment.
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The challenge is to establish a design process and discipline across a complex design chain that populates and maintains the content of the co-design environment as a natural byproduct of the various component design processes. This is a lesson learned from the enablement of the SoC design environment (IP design reuse). It is too costly and time consuming to develop reusable data after the fact.

Technology Libraries. For every design technology referenced in the design, a technology file must be created to represent the complete manufacturing layer stack-up and all of the associated design rules for that design process. Each component to be co-designed as a part of the overall design will be associated with its technology file.

IP Libraries. Each reusable design component must have an abstract component model that is sufficient to represent the component for implementation and analysis during the design process. The details and accuracy of this abstract contain the quality of results. A complete component abstract must include all of the required physical, logical, electrical, and manufacturing data and attributes to fully implement the component into a design.

Component abstracts consist of:

  • Geometries required to sufficiently describe the physical device to the tools in the design flow for placement, routing, and DFM rule checking. Inclusive of the geometric attributes of height, width, and length; constrained regions such as voltage; location and attributes or the geometries representing the connection areas; etc.
  • Formal constraints and properties that provide component use model information to the tools in the flow to achieve design coverage (ie. coupled impedance constraints for a differential pair).
  • References to models that represent the various component behaviors to tools in the design flow (ie. IO buffer simulation models).

An IO library is a special class of IP library that contains IO buffers. IO buffers are specific to both a design technology and, most often, a communication interface. There also should be sufficient data to determine the use model for each buffer, such as design constraints, signal specifications, and characterization data.

Design Guidelines. To provide predictable and consistent design results, each design house should have a set of guidelines and general rules defined. A portion of the rules should be prepared (at least templates) to help define the field of use for the referenced tools and flows used in the design process.

Package Libraries. One of the first steps in a design process is to perform package selection. To enable this function, there must be a model for each package to be evaluated. The model should consist of cost, as well as physical, thermal, and electrical specifications, simulation models, and constraints.

Other Components. There are many other types of components or other data relative to the content of a design that must also be modeled. Some examples include MEMS devices, shielding, insulators, and spacers/interposers.

Co-design Process

The scope of this article is concerned with the use of concepts and challenges of co-design, therefore the details around SoC and PCB development will not be treated in depth, nor will standard IC packaging.

To simplify the discussion of co-design design challenges, we will discuss a 3-part design process: system exploration, specification and analysis, and system integration.

Customers have their own design process that consists of a number of parts. These high-level stages were chosen based on the need to demonstrate clear differences between data quality and design objectives for major portions of the design process. The term “design concept” refers to the implementation concept for the physical structure of the design. Factors to be considered include: components embedded in the substrate interconnect vs. placed as discrete components and various combinations of flip chips or wire bonded chips placed in a variety of stacked and side-by-side configurations.

System Exploration. This is the initial phase of design in our concept. Once the design architect has a general idea for a new system, a system implementation concept must be developed. First, the system architecture is partitioned into a set of implemented components that will form the system. These design partitions should be targeted to an implementation fabric, such as a SoC, a MCP, or a PCB (Figure 2).

Figure 2. System exploration.
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Design complexity and previous experience with this design configuration determines the amount of effort and energy that is put into this design process. For this discussion, reasonable complexity and uncertainty are assumed.

The amount of design data may be limited to abstract models. If a design component already exists, then it should be modeled in the co-design environment and properly referenced by the architect, otherwise an abstract model of that component should be created. The completeness and accuracy of these models should match the design complexity and risk, and be sufficient to ensure that the design concept will meet objectives.

Specification and Analysis. Once a design concept (or short set of concepts) has been defined, the designer then develops a detailed plan for each component within the design (Figure 3). Some of these planning efforts may be performed across the design chain. For instance, a SoC designer may have tight design constraints and must complete an initial design plan (using the concept abstract if available and applicable) that would be delivered back to the designer. Other planning efforts may be performed directly by the designer and delivered out to the specific component designer.

Figure 3. Specification and analysis.
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Once a detailed plan exists for each component in the design, the placement of each component, the assignment of all IO, and detailed electrical analysis can be performed. During the system exploration stage, only cursory analysis with incomplete models is performed. This creates an executable specification for the physical and electrical interfaces of each component. These specifications are used to control the implementation process of each component and its integration into the design.

Design Objective. To validate the design assumptions and develop an executable specification for the design and its components, the following is required:

  • An accurate physical abstract, including die area, scribe area, saw line, and accurate IO placements with logical assignments.
  • Complete virtual system interconnect model with full physical assignment from IO buffer of a component to package, extracted and estimated wire models, fully constrained wire topologies, and IO buffer models.
  • IO test bench developed with constraints for any new buffer under design and process characterization.
  • Defined DFT architecture, with DFT interface specifications clearly defined for each component.
  • Realized design concept that passes manufacturing checks.
  • Top-level functional simulation driven from the design’s golden netlist.

System Integration. Now that detailed planning and early analysis have been completed, detailed implementation can begin. In the design process suggested here, the design of each component is always done in the context of the whole system, even if a portion of that system (for instance, the PCB) is to remain in virtual form (Figure 4).

Figure 4. System integration.
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The greater co-design chain will be used to implement each component. The system integrator will import all of the completed design components and integrate them back into the design, drive the completion of the design itself, and ensure that all analysis is repeated and sign-off for manufacturing is achieved.

Throughout the implementation process, the design must be optimized and change must be controlled between components and the design itself. The system’s integrator is responsible for the management and arbitration of all of these changes. This ensures that the design is always current with the implementation of each component, and vice versa.

Design Objective. To complete the implementation of the design and release it for manufacturing, all of the physical implementation must be completed; the VSIC model must be populated with extracted interconnect models across all components and fabrics; electrical sign-off is necessary for power and signals; manufacturing and assembly sign-off must be complete; and final logical and functional verification based on the VSIC netlist must be complete.


The value of co-design is being able to optimize two or more design fabrics as a concurrent process. Of course, such inter-fabric editing and optimization requires a robust ECO process so that the different design teams remain synchronized when manipulating common design data. Apart from physical design optimization for routability, signal integrity, and manufacturability, the designer must ensure that the package meets thermal performance/stress constraints. Designers must also provide the PCB design team with a signal integrity simulation model of the package that includes accurate modeling of 3-D structures for the critical signals and ensure that it is accurate at the typical operating frequencies the package will experience. It is obvious that designing, optimizing, and validating a complex, multi-component package is not a simple task, but having a well-integrated set of design tools that enable cross-fabric co-design optimization is the only real path to widespread co-design adoption.

KEITH FELTON, product marketing group director, may be contacted at Cadence Design Systems Inc., 270 Billerica Road, Chelmsford, MA 01823; (978) 262-6464; e-mail: