Evolution of Organic Flip Chip Packaging
Packaging Technology Ready For Change
Organic flip chip packaging has come of age. It has evolved into a mainstream and mature technology that offers many compelling performance benefits. Drivers such as performance, cost, I/O density, and thermal impedance have at various times pushed flip chip designers in different directions to develop suitable solutions. To address these market forces, advances in design methodology, materials, and manufacturing processes have kept up with changing customer demands to enable laminate flip chip packaging. Improvements can be made in the following areas: co-design, substrate design and technology, and assembly technology.
Traditional flip chip package designers were tasked with offering “one size fits all” substrate designs. While generic designs are still popular and offer some benefits of cycle time and cost, today’s package designs are highly optimized to suit the end application. Signal integrity engineers play a more active role in judging design trade-offs while working closely with end customers to model package-level signal parasitics and associated system implications.
Silicon designers also are entering the fray. This co-design methodology integrates competing requirements from package designers, circuit designers, and silicon process engineers with a goal to deliver a “right the first time” packaging solution.
Substrate Design and Technology
Early flip chip substrate designs were seldom optimized for signal impedance control. Line width, space, and via rules were merely tailored to meet vendors’ capability, with a goal of achieving the highest possible process margin. While a robust manufacturing process today is certainly desirable, every signal trace now is designed with controlled impedance and, if required, differential impedance with its neighbor. Stripline and microstrip designs are further optimized to provide effective return current Vss referencing. Special traces are identified and modified to reduce cross talk and line resistance, or provisions made for shielded clock’s lines and PLLs.
Figure 1. Packaging Co-design flow.
Substrate design also has been about a constant tug-of-war between I/O density and cost. The more complex the design, the more aggressive the line and space rules are used - leading to decreased manufacturability, yields, and cost increases.
During the excesses of the late ‘90s, it appeared that density and performance were winning out. Customers anticipated a booming communications market to drive insatiable demand for faster, bigger, and more powerful computing and networking gear. This, in turn, drove suppliers to offer packages with pin counts of as much as 2,500 and body sizes up 52.5 mm. Although a definite niche still exists for such packaging technologies, today a discussion on substrate technology rarely ignores the elephant in the room: cost.
An age-old dilemma of juggling cost and performance can lead corporations to offer two different flip chip packaging product lines. A low-cost, 4-layer laminate flip chip version using 0.4-mm core technology, and a high-performance, enhanced version that uses traditional 0.8-mm core with up to 10 metal layers. This dual technology offering enables flip chip to participate in different market segments.
Vertically integrated semiconductor companies have already outsourced or are in the process of outsourcing manufacturing operations to subcontractors to focus on their core competencies. Flip chip process engineers who previously developed processes at an on-shore pilot line, and then transferred the technology offshore are now working directly with offshore subcontractors to develop and deploy new assembly processes and materials. Development cycle times have been squeezed in response to pressures on time-to-market.
Not to be left behind, material suppliers such as underfill and substrate producers form an integral part of the development team that involves several levels of the supply chain, including OEMs, CMSs, IDMs, and SATS. This enables all parties to quickly digest end-customer requirements to produce candidate materials with the highest probability of qualification success, while at the same time focusing on manufacturability and cost. This just-in-time R&D helps reduce multiple cycles of learning.
On the assembly materials side, Cu metallization and low-k dielectrics in silicon have added their own challenges. Underfill material properties become even more critical in their dual role as stress reducers to the low-k layers, as well as to solder bumps. Wafer dicing improvements typically geared toward reducing street widths to maximize wafer use are now targeting reducing stresses in the brittle, low-k dielectric layers.
Lead-free legislation is driving further improvements in underfill materials. A recent RoHs waiver may allow IDMs to ship components containing greater than 85% lead content. This is having the opposite effect of driving some solder bump users to increase the lead content in their solder bumps.
If the recent proposal requesting a complete waiver for the lead content in flip chip bumps passes, companies may be able to do an about-turn and return to eutectic tin/lead bumping.
Efforts to take costs out of flip chip assembly are progressing on many fronts. Process and material standardization across multiple sites has the added benefit of reducing risk. While process improvements increase throughput and yield, equal attention is devoted to reducing subcomponent costs, such as heat spreaders and stiffeners.
Figure 2 outlines the evolution of heat spreader designs in flip chips. A Ni-plated stiffener and heat spreader combination has given way to a single piece stamped heat spreader. Further simplification of the manufacturing process, reducing machining steps, enables a one-piece top hat from a single stamping operation. Future improvements may include strip format overmolded substrates with drop-in heat spreaders or simply bare die with direct attachment of heat sinks. Simplifying manufacturing processes for heat spreaders and eliminating stiffeners can provide opportunities for cost savings.
Figure 2. Evolution of heat spreader designs in flip chip packages.
Cost reduction efforts are sometimes hindered by long cycle times in evaluating and qualifying changes with the end customer. Early engagement with the end customer may help curtail part of this long cycle.
Requirements from customers have evolved as well, and become more sophisticated. End customers are cognizant that 1st-level material or process changes may affect downstream 2nd-level performance. As a result, an all-encompassing, board-level qualification methodology had emerged that requires substrate suppliers and other material vendors to simulate board handling and use conditions through 4-point bend testing, and shock and vibration tests, in addition to traditional tests like temperature cycling. While the development cycle has become smarter, the qualification cycle has become longer and more complex.
Today, advances in laminate flip chip packaging only offer incremental evolutionary benefits. The primary drivers have traditionally been the same, though they may change in priority from time to time. The R&D model also has evolved to meet the demands of the marketplace. Organic flip chip packaging appears ready for a revolutionary change.
YOGI RANADE, product marketing manager, may be contacted at LSI Logic, 1621 Barber Lane, Milpitas, CA 95035; (408) 954-3406.