Packaging Trends for the Next 10 Years
Having been involved in the iNEMI roadmaps, recent workshops organized by the NNI, SRC and NSF, and discussions with semiconductor and packaging folk, it’s apparent that the semiconductor folks have figured out what’s going to happen in the next 10 years. Moore’s Law is going to run out of gas because we are starting to hit feature sizes where quantum effects become dominant, and leakage effects mean that efficiency and reliability suffer. At the 90- and 65-nm leading-edge nodes at the moment it’s not a problem, but when we dip through the 22-nm node and some features start to be below 10-nm in size, we’ll hit a basic property of physics. The wavelength of an electron (which we all remember from quantum mechanics has a problem remembering whether it’s a particle or wave) is around 10 nm. Once two conductors are only a nanometer apart, an electron has an equal probability of being in either one!
So, how are we going to deal with it? Looks like the industry will take a two-pronged approach: look for the replacements for CMOS, and also see what we can do to drag out the last drop of performance from CMOS.
Let’s look at the new technologies. They’re uncomfortable to many of us with a classical materials background. They will involve biological elements, molecular-directed assembly, and direct optical switching. This translates to a real packaging challenge - as we move toward systems that emulate the most effective computer (your brain) from supercomputers that have the intelligence currently of something you might squash with your foot, we move inexorably toward room-temperature assembly.
Another characteristic of the biological system is directed assembly. Using proteins and modified cell and other structures, it is possible to interconnect devices at low temperatures with selected links that can then be plated. Self-assembly is critical, but must conform to semiconductor infrastructure - low-temperature wiring of structures for sensors or transistors by nano cluster deposition is also a great alternative way forward. Here, atomic clusters produced in a vacuum chamber fall into lithographically prepared V-grooves and, then, because of their surface energy, spontaneously weld together.
Packaging in the new technology area will involve low-temperature interconnect through adhesives - possibly UV cured - with nano-sized conductive fillers. We anticipate that the use of carbon nanotubes as conductive additives or hook-and-loop fasteners is possible, and we may be dealing with nanofluidics and integral optics.
When we look at conventional packaging, the usual cry from customers is “It’s too big, it can’t get rid of the heat, and it costs too much!” This is provoking a number of trends:
- Putting more into packages (stacked die) or modules to minimize size and packaging cost and increase speed.
- Moving to modules (the borderline between packages, modules, and daughtercards is getting more and more diffuse) to bring processor and memory physically closer together, as well as combining analog and digital functions for speed and cost. We can expect a “dumbing-down” of the motherboard.
- Conventional wisdom is that a SiP or module will always evolve to SoC. This has happened with some modules, e.g. Bluetooth, but there is a volume and flexibility tradeoff, and many modules will remain modules.
- We expect to see novel short-distance interconnections and packaging structures, including “overhead” systems separating power and fast signal lines, and direct optical links to increase speed.
- Moving toward flip chip on board to reduce size and cost. There are technical and yield barriers, but the economic incentive is growing.
- Changing architecture to modify heat evolution, such as using dual processors to carry out operations in the same time as a blazing fast single processor with impossible heat evolution would take, and using liquid cooling as in the new Apple PowerMac.
- Lower temperature assembly. We just raised it to go lead-free, but my friends in Japan tell me that once the metallic lead is out of the component supply chain (bad things happen when lead and bismuth are both present) they plan to switch to lower-temperature solders containing Bi or Zn alloys.
So who are the winners in this period of change? Innovative packaging houses with the flexibility to adapt to chip-on-board, module packaging, and innovative design. And let’s not forget that we’ll be making a lot more conventional packages in 10 years than we are today!
ALAN RAE, Ph.D., VP Of Market and Business Development, may be contacted at NanoDynamics Inc., 901 Fuhrmann Blvd., Buffalo, NY 14203; (716) 853-4900 ext. 346; e-mail: email@example.com. Rae also holds the positions of Director of Research for iNEMI and chair of the JISSO North America Council.