Influence of Design on Package Assembly


Substrate design is largely driven by the performance requirements of a package and the fabrication limits of the supply chain. However, considerations of package assembly and the influence of design decisions on package yield are critical to consider, particularly for flip chip devices. Interconnect yield, interconnect voiding, and underfill voiding are all directly affected by design decisions.

Consider an example of the flip chip assembly processes using “no-flow” underfill materials in which the formation of underfill voids is directly affected by the substrate design and substrate surface topology. The no-flow flip chip process has significant potential to displace conventional flip chip processes for consumer electronics and mobile applications. Reasons include the elimination of processing steps, reduction of process complexity, reduction of capital equipment requirements, reduction of equipment maintenance, and enhancement of process robustness.

No-flow underfill is an attractive option because it greatly reduces the amount of processing steps and, therefore, the processing time needed. The no-flow process typically begins with dispensing or printing no-flow underfill onto the center of the chip bond area. The flip chip is then placed in the middle of this area, compressing the underfill deposit and allowing the flip chip bumps to make contact with the substrate bond pads. Assembly process forces are well within the ranges capable in standard pick-and-place systems. Finally, the assembly is placed in the reflow soldering oven to solder connections between the flip chip and the substrate.

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Several parameters have a high probability of affecting voiding in no-flow processing. Substrate design variables such as interconnect pad height, soldermask height, pad to soldermask separation, and pad pitch potentially increase voiding in the underfill. Processing parameters such as chip placement speed, underfill viscosity, and deposition geometry also affect the flow front speed and can increase voiding in the underfill.

To study the effects of substrate design features, a series of test vehicles was fabricated. The above factors were varied over 3 to 10 levels on the test vehicles to study their effect on underfill voiding. To simplify the voiding analysis, glass chips were used to simulate flip chips. The chips were assembled using standard no-flow underfill assembly processing steps. Void count and location were analyzed with respect to each design factor.

The factors influencing void formation in no-flow underfill processing include both substrate design factors and assembly process parameters (See Figure). Key factors include the soldermask thickness above the interconnect traces, the separation distance between interconnect pad and soldermask opening, pad shape, feature shape, and flip chip placement velocity.

Underfill voiding is effectively minimized by minimizing the thickness of the soldermask, minimizing separation distance between interconnect pad and soldermask opening edge, and placement velocity. Metal-defined pads should be fabricated with minimal soldermask thickness using mask-defined pads and minimal interconnect pad heights. Circular interconnect pads and soldermask openings also tend to minimize the numbers of voids that remain near the pads.

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It is important to consider substrate design features during package design to minimize package assembly defects and maximize assembly yield.

DANIEL F. BALDWIN, president, may be contacted at Engent Inc., 3140 Northwoods Parkway, Suite 300A Norcross, GA 30071.