Choosing the Right Thermal Interface Material
In the thermal management of microelectronics, the interface material layer between a chip and heat spreader presents the single largest barrier to heat flow in the packaging of high-power dissipation devices. The selection of a suitable material to fill the interface between a chip and a heat spreader is critical to the performance and reliability of the semiconductor device.
Interface materials reduce the contact resistance between the mating heat-generating and heat-sinking units by filling voids and features created by the non-smooth surface of the mating surfaces. Several factors affect the performance of a thermal interface material (TIM) layer in a device. While bulk thermal conductivity of a TIM is a commonly used differentiator in the selection of a TIM for a microelectronics application, other factors such as the ability to achieve the required bondline thickness, provide low interfacial or contact resistances, and possess long-term performance reliability also are of critical importance. Depending on the application and the TIM type, structural strength, dielectric properties, volatile content, and cost may need to be factored into the TIM selection process.
Thermal Interface Materials
A cross-sectional view of a flip chip device with a heat spreader and heat sink attached is shown in Figure 1. The thermal interface layer between the chip and the heat spreader typically is designated as “TIM-1,” and the TIM layer between the heat spreader and the heat sink is usually designated as “TIM-2.” Several material solutions exist that can perform the functions of a TIM-1 or a TIM-2 - adhesives, greases, gels, phase change materials, and pads. There are certain advantages and disadvantages associated with each of these TIM solutions. Most TIMs consist of a polymer matrix, such as an epoxy or silicone resin, and thermally conductive fillers such as boron nitride, alumina, aluminum, zinc oxide, and silver.1 In this article, examples of adhesive systems are discussed in detail, however, the principles are applicable across other TIM systems.
Figure 1. TIM-1 and TIM-2 layers in a flip chip device.
Thermal Adhesives. Thermal adhesives are particle-laden, one- or two-component materials that typically are applied via dispensing or stencil printing. Adhesives are cured to allow for cross-linking of the polymer, which provides the adhesive property. The advantage of thermal adhesives is that they provide structural support, therefore eliminating the need for mechanical clamping.2
Thermal Greases. Thermal greases typically are silicone oils that are loaded with thermally conductive filler. Thermal greases do not require curing and have the ability to flow and conform to interfaces. They also offer reworkable thermal interface layers. On extended operation and over time, greases can degrade, pump-out, or dry out, which causes the thermal performance of the TIM system using the grease to suffer significantly.2,3
Thermal Gels. Gels are low modulus, paste-like materials that are lightly cross-linked. They perform like a grease with respect to their ability to conform to surfaces, while displaying reduced material pump-out.2
Phase Change Materials (PCMs). PCMs undergo a transition from a solid to a semi-solid phase with the application of heat. The material is in a liquid phase at die-operating conditions. PCMs offer several advantages including the ability to conform to the mating surfaces and no curing.2,3
Thermal Pads. Thermal pads usually are fabricated by molding non-reinforced silicone with conductive fillers. Reinforcements for thermal pads can include woven glass, metal foils, and polymer films. Thermal pads are pre-cut and offer gap-filling functionality. They possess limited thermal performance, however, and are sensitive to the pressures applied.2,3
Performance of Thermal Interface Materials
There are several performance metrics that are used to describe the thermal performance of a TIM - thermal conductivity, apparent or in situ conductivity, thermal resistance, thermal impedance, etc. Thermal conductivity is a material property that describes the ability of a material to conduct heat after the heat has entered the material. Apparent or in situ conductivity, however, takes into consideration the interfacial or contact resistances between the TIM layer and the interfaces. Apparent or in situ conductivity is a more accurate representation of the performance of a TIM layer. Thermal resistance and impedance typically are used interchangeably. However, they both represent the resistance to heat flow across the interface. Units of °C/W or mm2 K/W (or in.2 C/W) are used to describe thermal resistance or impedance. The mm2 K/W (or in.2 C/W) value is the °C/W when normalized over the contact area. Thermal resistance across a TIM layer is an accurate indication of its performance in a device.
Figure 2. Cross section of a TIM layer.
The total thermal resistance (or in situ thermal resistance) offered by a TIM layer consists of the bulk thermal resistance and the contact resistances. Figure 2 shows a cross section of a TIM layer between two surfaces. The bulk and interfacial regions are shown. The bulk thermal resistance is a function of the bondline thickness (BLT) of the layer and the bulk thermal conductivity of the TIM. Contact resistances exist at the TIM-semiconductor device and TIM-heat spreader interfaces. The interfacial (contact) resistances depend on the surface characteristics of the mating surfaces and the ability of the TIM to flow into surface features and form a void-free and non-filler depleted TIM layer at the interfaces.4 Another contributor to interfacial thermal resistance is phonon scattering, arising from dissimilarities in material properties between two interfacing materials.5 The thermal resistance across a TIM layer can be decreased by reducing the bondline thickness of the TIM layer, reducing the interfacial thermal resistances, and increasing the bulk thermal conductivity of the TIM.
Measurement of In Situ Thermal Performance
While developing and using a TIM, a measurement system must be in place that can accurately measure the system-level or in situ performance of the TIM layer. A measurement system that provides only the bulk thermal conductivity of the TIM presents an incomplete understanding of the performance of the TIM in an end-use environment. Figure 3 illustrates such an example by plotting the in situ thermal resistance and bulk thermal conductivity of 5 TIMs. All TIMs were assembled and measured under similar conditions. With an increase in bulk thermal conductivity, a reduction in in situ thermal resistance is expected. However, this is not necessarily the case all the time. TIM-C has lower in situ thermal resistance than TIM-D and TIM-E, both of which have higher bulk thermal conductivities. In addition, TIM-B and TIM-D have similar in situ thermal resistances, while the bulk thermal conductivity of TIM-D is nearly twice that of TIM-B.
Figure 3. In situ thermal resistance and bulk thermal conductivity.
There are several commercial and company-specific thermal measurement systems based on ASTM standards. A thorough understanding of the measurement capabilities and their associated uncertainties is critical to the accurate interpretation of the thermal data and its extrapolation into an actual device environment.
A laser flash diffusivity method (based on ASTM E-1461) can determine the in situ thermal conductivity and thermal resistance values. This transient method enables measurement of single-layer and multiple-layer samples.6 The in situ or effective thermal resistance of the TIMS is measured using a 3-layer sandwich sample. The TIM is applied between two 8-mm × 8-mm coupons that represent the characteristics of the mating surfaces in the device. A short laser pulse heats the sample and the resulting temperature rise on the rear surface is measured with an infrared detector. By analysis of the resulting temperature vs. time curve, the thermal diffusivity of the TIM layer can be determined. The thermal diffusivity value is used to calculate the in situ thermal resistance of the TIM layer.4,6
Junction-to-case thermal resistance or θjc is a widely used industry measure of thermal performance of an electronic package. θjc value typically is used to compare the thermal performance of different electronic packages housing similar IC devices, or to compare different IC devices in a similar package housing (EIA/JESD51-1). Thermal die with diode temperature sensing networks are used to obtain θjc values. The thermal die is heated by driving a current through a doped silicon well between a pair of bus bars. The junction temperature can then be obtained by measuring the voltage across the series of diodes. The diode network voltage as a function of junction temperature is calibrated to obtain the diode calibration factor. A heating power is applied to the device, and the case temperature (temperature of the heat spreader top surface) is measured on stabilization. The difference in temperature between the junction and the case divided by the heating power gives the thermal resistance, θjc.
TIM Layer Performance Factors
A thorough understanding of the various factors that affect the system-level performance (thermal, mechanical, electrical, etc.) of a TIM can be invaluable for material development, TIM selection, and optimum use. A concise, “fishbone” diagram is shown in Figure 4, which presents some key factors that affect the system performance of a TIM. The choice of appropriate performance metrics is of critical importance. The in situ resistance (sum of bulk and contact resistances) of the TIM layer is a more accurate and appropriate performance metric than bulk thermal conductivity of TIM. For example, the characteristics of the mating surfaces or the assembly conditions have no effect on the bulk thermal conductivity of the TIM layer. However, they are the primary factors that determine the interfacial thermal resistances and BLT (in turn, bulk thermal resistance).
Figure 4. Factors affecting TIM system performance.
Figure 5 plots the in situ thermal resistance vs. BLT of 3 TIMs, when assembled using different assembly conditions. The TIMs have similar bulk thermal conductivities, but different filler or resin characteristics. While possessing similar thermal conductivities, the TIMs achieve different BLTs at different assembly conditions, possess different interfacial thermal resistances, and display vastly dissimilar in situ thermal resistance numbers. Key filler characteristics that affect in situ thermal performance are the filler type, shape, and size, as well as filler loading and the treatment of the fillers during the TIM formulation process. The type of resin system, its ability to wet the particles and the surfaces, and the interaction between the resin and the filler also can affect the in situ performance of a TIM.
Figure 5. Effect of filler and resin characteristics.
For a given TIM, there exists a set of assembly process conditions that can be used to reduce the total thermal resistance of the TIM layer. Figure 6 shows the in situ thermal resistance of 6 different TIMS when assembled using “standard” assembly conditions and “optimized” assembly conditions. There is significant increase in thermal performance with the optimized assembly conditions. Different TIMs respond differently to assembly conditions. For example, TIM-1 has a higher thermal resistance than TIM-2, TIM-4, and TIM-5, when assembled using standard assembly conditions. However, when the assembly conditions are optimized for each TIM, TIM-1 has lower thermal resistance than TIM-2, TIM-4, and TIM-5. The assembly process conditions that will be used in the microelectronic package and the range of process conditions that are acceptable must be established before the selection of a TIM. While highly loaded TIM systems offer high bulk thermal conductivity, they also are highly viscous and may not be capable of achieving thin BLTs at low assembly pressures - presenting a high thermal resistance path.
Figure 6. Effect of assembly process conditions.
The above examples bring to the forefront the importance of measuring the in situ thermal resistance of a TIM layer at assembly conditions and between the surfaces that will be used in the device (or during packaging). While some of the factors shown in Figure 4 affect the performance of a TIM layer independently, the interactions of two or more factors may have a significant effect on the system performance of the TIM layer.
During device operation, the TIM layer between the silicon device and heat spreader/sink is subjected to thermal and mechanical stresses due to differences in thermal expansion coefficients of the silicon devices and the heat spreader material. Depending on type of TIM system, different failure mechanisms may arise. An adhesive TIM layer can delaminate and lead to the formation of air gaps at the interface of the TIM layer and the mating surfaces, increasing thermal resistance. A grease layer may pump out, bleed out, or dry out during the course of device service life. A gel may harden and no longer conform to features on the heat spreader surfaces. Degradation of the TIM layer during the operating life of a device can shorten the life of a device and limit its performance. Accelerated reliability tests (air-to-air thermal shock, temperature/humidity exposure, high-temperature storage, etc.) can determine the reliability performance of a TIM layer. Several factors affect the reliability of a TIM layer. In addition to the operating conditions, the geometry of the TIM layer (BLT, area of contact), resin material; heat spreader and chip surface characteristics; filler type and loading can all have an effect on the reliability of a TIM layer.
Choosing The Right Material
The choice of a TIM for a particular application involves the consideration of various factors, of which performance, manufacturability, and cost are primary ones. Desirable TIM characteristics include:
- Low in situ thermal resistance: high bulk thermal conductivity; ability to achieve low BLTs under actual assembly conditions; and low interfacial thermal resistances when applied between actual (end use) surfaces.
- Adequate adhesion if structural support is required.
- The ability to maintain thermal and mechanical performance throughout the life of the device.
- Easy to process in a manufacturing environment.
- Other factors such as low volatiles, dielectric properties, storage conditions, shelf life, pot life, toxicity, etc.
The TIM layers between a chip and a heat spreader and between a heat spreader and a heat sink are critical to the performance and reliability of microelectronic devices. A thorough understanding of the performance metrics, factors that affect the performance of a TIM, and the techniques to enhance the performance of a TIM layer can facilitate the selection of the right material solution for your cooling problem. It also is important to select a material that meets your requirements, not only when it is first used in a device, but throughout the life of the device.
- Mahahan, R., Chiu, C-P., and Prashed, R., “Thermal Interface Materials: A Brief Review of Design Characteristics and Materials,” Electronics Cooling, Vol. 10, No.1, 2004.
- Prismark Partners LLC., “Thermal Interface Materials: Cool Materials for Hot Products,” September 2001.
- Viswnaath, R., Wakharkar, V., Watwe, A., and Lebonheur, V., “Thermal Performance Challenges from Silicon to Systems,” Intel Technology Journal, Q3, 2000.
- Campbell, R.C., Smith, S.E., and Dietz, R.L., “Measurements of Adhesive Bondline Effective Thermal Conductivity and Thermal Conductance Using the Laser Flash Method,” 15th IEEE SEMI-THERM Symposium, San Diego, CA, 1999.
- Hasselman, D.P.H., Donaldson, K.Y., Barlow, F.D., Elshabini, A.A., Schiroky, G.H., Yaskoff, J.P., and Dietz, R.L., “Interfacial Thermal Resistance and Temperature Dependence of Three Adhesives for Electronic Packaging,” IEEE Transactions on Components and Packaging Technologies, Vol. 24, No. 3, 2000.
- Campbell, R.C., and Smith, S.E., “Flash Diffusivity Method: A Survey of Capabilities,” Electronics Cooling, Vol. 8, No. 2, May 2002.
ARUN GOWDA, electronic packaging engineer, SANDEEP TONAPI, electronic packaging engineer, may be contacted at GE Global Research, One Research Circle, Schenactady, NY 12309. BRAD REITZ, Global Application Engineering manager, and GREGORY GENSLER, application development engineer, may be contacted at GE Advanced Materials - Silicones, 260 Hudson River Road, Waterford, NY 12188.