Issue



3-D Partitioning of Printed Circuit Design


02/01/2005







‘ELEVATED HIGHWAY BYPASS’ PACKAGING DESIGN

BY JOSEPH FJELSTAD, GARY YASUMARA, AND KEVIN GRUNDY

The design and manufacture of circuit assemblies have gone through several definable eras since the invention of the PCB. Early PCBs were relatively simple, designed primarily to replace discrete wire interconnections between simple devices. With the introduction of the IC, however, there came increasing complexity, and the single-sided board evolved to use the second side for circuits, power, and ground distribution. Shortly after, the plated through-hole era began. Further advances in IC technology and the desire for increased functionality gave rise to the concept of the multilayer board, wherein power and ground were distributed on internal layers and interconnected by plated through-holes.

Multilayer technology remained fundamentally unchanged for nearly 20 years, but was punctuated with incremental but innovative changes such as the buried via, which helped to further increase board density, functionality, and ease of assembly. In the early to mid 1990s, high-density interconnect (HDI) technology debuted as the successor to the more expensive multichip module (MCM). This technology was marked primarily by the presence of microvias, produced either by photolithographic or laser technologies, which paved the way to greater circuit density capability. Since the introduction of HDI, there have been a host of new board construction technologies that provide the increased interconnection density to solve the problems of routing. Other technologies will be tapped to help include the embedment of passives and use of distributed capacitance layers in the board.


Figure 1. The evolution of the printed circuit has been paced by the demands of IC technology.
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A more recent design response has been to create a system-in-package (SiP). This technology is a rebirth of the MCM, because it shares many of the characteristics of the earlier, ill-fated solution. Once again, the technology is fundamentally targeted to increase density to yield greater functionality per unit space and greater localized performance. From a density perspective, solutions to date have been impressive. For example, leading-edge SiP devices include 8 or more chips integrated in their construction. While most SiP solutions have been related to increasing functionality and reducing volume, while lowering cost, higher performance remains a never-ending priority in electronics. These multichip package structures have met the challenge of higher interconnection density, but unfortunately have not addressed the challenge of meeting the signal integrity requirements for higher speed, relative to their interconnection on the circuit boards to which they are joined. There is a need for new approaches to designing and manufacturing interconnections to meet the future needs of high-performance electronic systems and desirably deliver those systems at lower costs.

Rethinking Chip Package and PCB Design

Chip-to-chip interconnection is the fundamental objective of electronics system board-level design. That basic task was further complicated in recent years, as the need for higher switching speeds are now a matter of increasing importance. The present and future challenge in interconnection design is to get higher performance at a lower cost. Compounding and expanding the scope of the problem is that the power density from all of the various high-speed signals is becoming significantly greater, and thermal management is simultaneously moving to the top of the problem list. Much to their credit, SiP developers are creating clever solutions for getting the heat out of these densely packaged silicon structures. Even so, SiP devices carry with them appreciable risk.

The resulting and seemingly never-ending tension between performance demand, product size and cost, and ultimate system reliability makes for difficult design choices. If the devices are relatively inexpensive and manufactured using mature and predictable semiconductor technologies, where likely infant mortality is known, SiP technology appears attractive. In cases where the IC dice are cutting-edge and expensive, however, system designers will want to be more conservative. Moreover, while handheld electronics continue to drive much of interconnection technology - owing to the demand for greater functionality in a small space. Such systems are open to other solutions that can provide the needed benefits in a cost-effective manner.


Figure 2. Standard PCB materials and processing methods have a significant number of potential impediments relative to high-speed signal processing.
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The convergence of clashing objectives has created significant challenges, but within those challenges lays the opportunity to rethink the long-held approach to circuit assembly design, and how and where chips are interconnected. Standard materials and design processes will no longer meet the performance needs for high-speed interconnections. While silicon technology continued to double performance every 18 to 24 months in accordance to Moore’s Law, copper interconnection technology was largely unchallenged until the processor transitioned into the multi-GHz range. Today’s PCB bus speed is pegged at 800 MHz using standard materials and design practices, because of the many features of concern commonly found in the signal path (Figure 2). Some relief can be found in exotic materials. They offer only temporary relief, however, and increase cost. There is relief by considering the design, manufacture, and assembly of PCBs. The solution is conceptually simple: route the highest-speed signals between chips designed to communicate with one another by using a more direct path through a controlled impedance channel. How can this best be done? Simple: establish signal paths in all 3-D of space.

‘Elevated Highway Bypass’ Packaging Design

While traditional PCB design has signals routed on, in, and through the PCB, another design approach* has signals routed both through and above the substrate with critical routes transmitted directly from chip-to-chip by controlled impedance interconnects mounted to the upper surface of the packages. This “elevated highway bypass” concept avoids traditional paths through the PCB for high-speed signals and the elements and features that contribute to signal degradation and poor high-frequency performance. A significant number of potential design feature and material and processing concerns in traditional board design and manufacture include: the metal conductor path, including its height, width, and length, and proximity to other circuit paths; the signal path’s various interconnection vias encountered of the circuit path. In addition, there are other interconnection elements such as connectors and solder joints that are capable of creating signal discontinuities and disturbances reducing performance capability. There also is the matter of signal skew that contributes significant routing challenges for designers trying to exactly match signal path lengths. Moreover, in high-speed signal propagation, the signal rise time is degraded because of signal loss in the materials of construction, manifest in the form of dielectric loss. Finally, conductor loss must be factored in, in addition to the numerous design features that can create impedance discontinuities previously accounted for.

These parasitic-inducing design artifacts have been of little consequence in lower-speed circuit applications, typically below 100 MHz. They are critical because signal speeds for digital systems enter the multiple GHz range. While improvements in materials and processes have yielded some performance gains, there is a need for improved methods to address the underlying high-frequency impediments.


Figure 3. A new design approach significantly improves performance and simplifies the construction of both package and PCB, while bypassing the parasitic effects associated with most traditional design layouts.
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This packaging design approach partitions the high- and low-speed design elements and routes them on different planes, with low-speed, power, and ground signals routed down through the package and into the PCB substrate, while the high-speed signals are routed directly off the top of one package to the top or tops of one or more other packages. The result is a high-performance interconnection path that does not require pre or post emphasis of signals. This is possible because of the clarity offered by the improved signal channel. Figure 3 provides a cross-sectional comparison of the old and new approaches. Figure 4 shows a comparison of simulation-based eye diagrams for the two different methods over a common distance of 3-in. at 25 Gbps.


Figure 4. The eye diagram comparison based on 3-D field solver simulation data shows an improvement is possible using the new design approach described in this article.
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Since the upper surface of typical chip packs is largely wasted space, except in cases where devices are designed for stacking to improve density, there is opportunity to use this space for selective interconnection between circuit devices that can benefit from high-speed signals. By analogy, while old methods route signals on the equivalent of city streets and subways (and high-rise buildings in the case of stacked packages), the new design allows signals routed on the equivalent of controlled impedance, high-speed, elevated superhighways - eliminating the circuitous and undulating circuit routes necessitated by traditional approaches. Perhaps the most obvious electronic interconnection medium for creating such a structure is a controlled-impedance, flexible circuit, although there are other manufacturable interconnection structures.


Figure 5. Use of the new packaging concepts provide reductions in signal skew and assuage many of the other challenges of high-speed circuit design by segregating high- and low-speed signals, thereby interconnecting simpler, more manufacturable IC packages and substrates.
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The new design likely will take time to become mainstream. As of now, there are no conventions or standards for such packages, even though IC packaging foundries generally see no significant challenge to manufacturing these devices. There is opportunity to use the technology today to have two or more IC chips communicate at native silicon speed. The design is shown in Figure 6, in which an existing package can easily be adapted to the high-speed task simply by attaching a rigid or flexible overlay extension to the surface of the existing package, ignoring the old signal paths and making direct connection from the chip to the high-speed bypass. This technique also allows for the addition of separate driver chips to boost performance for longer-distance transmission. Such devices may take the form of pre-tested IC packages joined and interconnected with another package.


Figure 6. Benefits of the new packaging design are realized using existing packages and mounting and interconnecting a controlled impedance circuit on top of a standard IC package.
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While the concepts presented in this article are presumably attractive for a range of applications, there are still a number of puzzle pieces that must be put in place before widespread adoption of the design occurs. With respect to the IC packaging design, there is a need to establish appropriate methodologies and protocols in different areas. For example, with respect to the I/O planning and sequencing, there are no tools that address the matter of considering the creation of high-speed interconnection between two distinct packages separately from those connections that are to be made through the PCB. With the new design’s approach, not all I/O are considered for interconnection at the same time. This requires a new methodology. Coordination of what is effectively two different designs must accommodate high-speed, fixed interconnections so that they can be considered once the packages are mounted on the PCB.

PCB design and manufacture may be less complex, because those steps have been relieved of the challenge of making the critical circuit paths. However, in PCB assembly, there will be some new challenges. For example, depending on the approach, IC package alignment may need to be tightened so that the flex circuit or other interconnection methods can connect reliably to one or more other packages once they are mounted on the PCB. There also will be a need to represent the top surface interconnections in 3-D space and, presently, PCB tools are 2-D. Still, in the realm of IC packaging, some of these 3-D issues are being addressed in stacked, wire-bonded structures.

Another area not yet discussed is that of electrical testing of IC packages and assembled systems. Testing procedures can be simplified with the new design. Providing unfettered access to high-speed signals makes full characterization of IC packages much less of a challenge and is an attractive alternative for future high-performance package validation.

Conclusion

The roadblocks to high-speed signal transmission from chip to chip can be addressed by a design approach to interconnection that takes advantage of the normally unused space that exists on IC packages. This method facilitates the creation of shorter, cleaner signal paths - offering higher performance at lower power, fewer-layer-count packages and substrates, and less costly systems. This alternative approach to design improves the performance of electronic products with minimal disruption to the manufacturing infrastructure. The move to high-speed interconnection requires rethinking the electronic industry’s standard approach to overall architecture. The partitioning of PCB circuit layout, segregating high-speed circuits from low-speed, power, and ground circuits is an approach that likely will be used in the future.

References

For a complete list of references, please contact the authors.
*Off-the-top (OTT) technology, developed by SiliconPipe Inc.

JOSEPH FJELSTAD, founder, GARY YASUMURA, Research & Development Engineering, and KEVIN GRUNDY, CEO , may be contacted at SiliconPipe Inc., 992 De Anza Blvd. #201, San Jose, CA 95129; (408) 973-1744; e-mail: jfjelstad@sipipe.com.