2005 AP Industry Forecast


As we begin 2005, back-end packaging is coming away from a profitable year. Most industry forecasters expect a moderate, cyclic decline in the upcoming year, followed by a slight recovery in 2006, and healthy expansion in 2007.

Advanced Packaging called upon the industry to give predictions for 2005, including new developments at their firms. The challenges are common: growing thermal issues, increasing densities, shrinking component size, continuing lead-free transitions, shifting global markets, and changing business issues.

Gartner Inc., a provider of research and analysis, predicts that the packaging and assembly equipment market will experience a 22% decline in 2005, with revenue of approximately $3.5 billion. However, to find out more about the packaging assembly and test markets, especially to take advantage of the pickup in orders by the end of 2005, an insight into leading firms would certainly help.

Gail Flower

John Lau, Lead-free Technical Program Manager

Agilent Technologies,
The implementation date (July 1, 2006) of the EU’s RoHS and China RoHS is fast approaching. I don’t think the electronics industry is ready yet. Thus, the most difficult challenges in electronics industry in 2005 will be converting all the SnPb components into lead-free components, and to standardizing the sample preparation for testing lead-free products.

John Boruch, President and COO

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Amkor Technology,
In 2005, Amkor will focus on maintaining a leading edge in the outsourced semiconductor assembly and test (OSAT) industry. Most leading subcontract assembly houses have evolved from focusing on mass production of standard packages, to providing customized packaging solutions. The latter has been driven by the pace and sophistication of consumer electronics and by the associated proliferation of higher lead counts, more complex materials sets, and innovative assembly manufacturing processes. Amkor is at the forefront of these trends. IC manufacturers look to OSAT companies for advanced packaging solutions and test technology development. Our customers seek technological capability and operational flexibility for marketing products faster at lower cost. We focus on high-growth areas: system-in-package (SiP); stacked packaging; flip chip and wafer-level packaging; strip test; and RF test. In 2005, Amkor will be integrating our acquisition of Unitive to create the industry’s leading provider of turnkey flip chip and wafer level packaging services; collaborating with electronics OEMs; and expanding our test capabilities.

It has become apparent that IDMs need liberation from the dual challenges of developing complex wafer-fabrication processes and rapidly evolving design, package, and test technologies and processes. This continues to be one of the most difficult challenges in electronics today from the perspective of IC manufacturing. Packages are becoming increasingly customized. Contract packaging and test houses are managing a greater number of specialized designs and material sets. Our goal is to deploy the right combination of resources to provide the best solutions at the lowest cost.

Mike Konrad, President

Aqueous Technologies Corp.,
We’re extending capabilities by purchasing a new manufacturing facility that is 50% larger than our current one. The larger facility will address the growth in cleaning created by a recovering economy and the implementation of lead-free.

Environmental issues present significant challenges to the de-fluxing industry. The reduction of VOC limits (implemented in Calif.), which prohibit the use of chemicals with VOC emissions greater than 25 g/L, challenge chemists and customers. Implementation of lead-free technology presents the greatest challenge. Lead-free solder pastes work best when components are clean.

Neil Mclellan, CTO

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We will focus on expanding our success in the QFN technology by bringing the TAPP (Thin Array Plastic Package), high-density L/F CSP, package into mainstream usage. This is supported by JEDEC approval, and we are expanding the supply chain for this new package, which offers low cost, high density, great thermals, strip testability, and excellent parasitics. Another focus is bringing the AirQFN, a cavity structure pre-molded package, on line. This allows application for high-speed RF products, MEMS applications, and light-sensing or emitting devices. This package format has a huge growth potential (high number of applications with high volumes in each). We believe AQFN will become the next family of ASSP packages.

The first challenge is co-design, from both a chip-package-system functionality, and design for test perspective, in both chip and package design. Shared design tools, such as Cadence APD, to import and share electrical parasitics and response curves across traditionally isolated development groups, will be key. Also important are design for test and integration of test access ports across the chip and package design process. The second challenge is thermal dissipation. As transistor density and switch frequencies increase, the thermal flux density of advanced die designs is expected to increase by 100% to 150% over the next year or two. The entire thermal supply chain needs to be considered, as box sizes and board spacing decrease. This means more and more heat has to be allocated to a smaller and smaller thermal budget across the system. Key to success here will be the step function increases in thermal dissipation of IC packages. We will be bringing up our “Metal Cap BGA” package that offers a 250% improvement in thermal dissipation compared to similar MOD PBGA products. The package will also offer reduced die level stress for compatibility with low-k and other fragile chip structures.

Mike Jamiolkowski, President

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Coventor Inc.,
The MEMS industry has awaken from a 2-year pause with increased corporate investment and launch of commercial products. We are also seeing growth in University R&D and integrated MEMS design. Sales in China, Japan, and India are growing steadily. We are expanding our existing MEMS design tools with CoventorWare 2005. We are also introducing new products that address integrated design issues such as packaging, chip stacking, 3-D modeling, and analysis. MEMS design tools are being looked toward as a platform for expanding technologies.

We are seeing that in the shrinking scale of chip design (90 nm and beyond) and in the growth of mixed technology that all processes in the design flow must be streamlined. There is a greater need for designers to consider interconnect, packaging, and proximity of device design.

Paul Walter, Managing Director

Dage Precision Industries Ltd.,
We will be rolling out new systems for production test and inspection needs of semiconductor packaging and PCBA, and will continue strong investment in primary R&D. We also will develop new processes, procedures, and systems with current customers. For example, emerging bumped devices and packages are creating several new failure modes that the existing test regimes are unable to screen. We are working to identify and analyze failures and to develop new test regimes. Internally, our x-ray manufacturing capabilities are being expanded in line with rising sales, and we have continued with our “cost down” plans, allowing us to bring more technology to customers at an affordable price.

One of the biggest challenges is the move to lead-free solder. Our bond test customers are concerned about intermetallic layers in bumped devices. This requires screening out latent failures at the bump/bond-pad interface. Lead-free joints exhibit more “after-aging” failures due to joint brittleness, so tests that screen for these issues would be a major breakthrough. We will introduce suitable systems to the market in mid-2005 for this. Lead-free requires examining joints for voids, opens, and cracks. With the introduction of ultra-high-resolution x-ray systems, we are able to clearly see microvoids that, after aging, can cause of cracks and opens.

Helmut Rutterschmidt, President

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Datacon Technology AG,
For our fiscal year beginning in April 2005, we expect worldwide revenue to grow 20 to 25%, largely due to volume sales of our new flip chip die bonders. We will also consider opening a new sales office location in the China market during our next fiscal year in April 2005 to March 2006. We also expect double-digit revenue growth in the auspicious U.S. market.

Peter Wiedner, VP Product Marketing

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Datacon Semiconductor Equipment GmbH
One could say that there are no new challenges in advanced semiconductor packaging. The major drivers, cost and higher-function density, do not change. Specific challenges will face packaging equipment suppliers, including meeting certain cost-of-ownership models, increasing demands for miniaturization, and being prepared for upcoming changes regarding materials. Flip chip technology has already been widely adopted for high pin count, high-frequency applications like processors, chipsets, and ASICS. The next challenge is the low pin count area, where cost is the only driver. To meet the demands of markets like flip chip on leadframe (FCOL) or flip chip on flex (FCoF), equipment suppliers will have to translate the technology to a much lower cost-of-ownership model. The goal is to offer the flip chip process at a price comparable to die attach.

Richard Heimsch, President

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At DEK, 2005 will be all about new technology. Not just in our traditional equipment segment, but also in stencils and new, high-accuracy mass imaging processes. The Micron Class is the newest machine platform and there are already two new models released based upon it. Our VectorGuard frameless stencil system will handle an increasingly wide range of materials and processes. Finally, our Internet-enabled service and support offerings open all new territory in real time interactive access to our process knowledge bases.

Sustaining the industry growth will be the ultimate challenge in 2005. Not to oversimplify, but the bulk of this cycle has been consumer-segment-driven. Business spending has been lackluster, and there is a lot of bearish sentiment out there about technology in general that could too easily become a self-fulfilling prophecy.

Michael J. Green, Business Manager, IC Packaging & Interconnect Materials

DuPont Electronic Technologies,
DuPont Electronic Technologies is focused on developing and supplying materials for high I/O, high-power packages like MPUs and low I/O, low-power packages like memory. Specific materials developments include embedded passive capacitor and resistor materials, microvia and redistribution dielectrics, bumping resists for wafer-level packaging, and thin substrates (both laminate and film). In development, consideration is given to thermal, electrical, and mechanical requirements to address lead-free soldering (high Tg materials), high-speed performance (lower dielectric loss materials), and reliability improvement (low CTE materials).

We see a number of challenges confronting the industry. We are addressing reliability in the flip chip package between the die (especially the low-k dielectric layer) and package substrate. We are developing material sets with improved thermo-mechanical properties. We are seeing continued drive to high density (<15-µm lines and space circuitry) and thinner packages (<1-mm), and our microvia dielectric and thin substrate materials developments are directly focused on this challenge. Another challenge is the high cost of developing new packages, and getting them to market quickly.

Ralph Henderer, Vice President

Entegris Inc.,
By using our materials science, manufacturing, and testing know-how, Entegris will be focusing on responsiveness - developing advanced resins, technologies, and respectful customer partnerships that directly impact customer profitability. We will continuing to be a leader in our global markets by delivering the products and services that best protect and transport critical materials required. A critical challenge for packaging will be achieving profitable business success in a cyclical industry. This will be determined by the industry’s ability to respond to steep upswings and downturns in the marketplace, while still maximizing profits throughout the value chain. Increasing environmental legislation, advancements in semiconductor fabrication processes, and customer or legislative requirements for traceability are just a few general issues facing our industry.

Lance Scott, President

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Owing to three very important industry trends (miniaturization, 3-D computed tomography, and the migration from film-based imaging), FEINFOCUS has agreed to be acquired by COMET to prepare for these newdynamics. This partnership gives COMET a better presence in North America, and FEINFOCUS a better presence in Asia.

Trends toward lower costs and higher I/O counts have driven the industry toward wafer-level packaging (WLP) and wafer-level chip scale packaging (WLCSP) techniques. Wafer bumping is one of the many challenges in semiconductor packaging. Bumping wafers is attractive because placing the bumps, or interconnects, directly onto the wafer offers efficiency and economy of scale compared to traditional single-die packaging techniques. High-resolution x-ray is emerging as a technology capable of exploring the true solder mass; thus, the potential voids beneath the bump surface are particularly important as the industry transitions to lead-free solders.

Patrick Trippel, President

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Henkel Electronics,
Lead-free and green materials are vital to our business and impact all of our materials, whether they are for PCBs or semiconductors. The need for materials to accommodate lead-free process temperatures is a huge opportunity for us. This opportunity exists because we already offer a complete solution for higher-level, 260°C-compatible, lead-free materials. On a corporate front, our continuing global expansion as part of our commitment to deliver local resources on a global scale, and a distinct emphasis on technical leadership, remains our focus for 2005 and beyond. I am excited to see some of the fruits of our labor materialize as we open our state-of-the-art Research and Application Center in Irvine, Calif. This is just one of many current and planned R&D centers for Henkel, matched by significant expansion in application support labs and personnel in Eastern Europe, Latin America, and Asia.

Henkel Electronics’ Hysol, Loctite, and Multicore materials have provided good year-over-year financial performance and paved the way for consistent growth going forward, but all suppliers need to provide more than just good products. It’s not about what you sell your customers, but what you do for them. Therefore, our objective is to continue to be vigilant in our quest to provide excellent value and expertise to all our customers. We also have the challenge of the infamous July 2006 lead-free compliance deadline approaching.

Brian Bauer, SMT Sales Manager

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Heraeus Inc.,
2005 will be an exciting time for Heraeus. The opening of our Technical Service Lab in late 2004 will allow us to better support our customers as well as develop enabling technologies. The lab is equipped with state-of-the-art equipment that will allow us to duplicate the production environment at our automotive, EMS, and semiconductor partners. In addition to this, Heraeus will be remain at the forefront of lead-free development and implementation by working closely with customers and consortia groups, such as NEMI, SPVC, and JG-PP.

The transition to lead-free will pose the biggest challenge. The ideal changeover would be from lead to lead-free without a middle step, but this is unlikely to happen. That transition phase will be problematic due to the mixing of technologies (leaded/non-leaded) and the complexities this will involve. A primary concern will be product labeling at all levels. Components and finished assemblies will need to be clearly marked. Where mixed technologies will be used, reliability of the assembly must be verified to ensure the desired product life and performance. In addition, rework or field repair must be considered when moving to lead-free, as it will be imperative that the right technology be used on the right assembly. The other major challenge in the U.S. will be the continued movement of jobs to lower-cost countries.

Joseph Bubel, President

Hesse & Knipps Inc.,
We are excited about the expansion of our production facilities. This will allow us to meet the customers’ delivery requirements, especially with our heavy wire bonder. Our BJ 715 and 815 have had software upgrades that meet the needs of our customers in the niche market of Al, Au, and Cu wedge-wedge bonding. We are starting to see the benefits of our aggressive marketing campaigns in both the Americas and Asia. Customers really are excited about our technology: wear-free bondheads, bond quality monitors, and process integrated quality control.

Certainly, some of the challenges we face in advanced packaging are in the areas of meeting fine-pitch requirements and providing solutions to customers who request wedge bonding outside of the normal Al and Au, such as copper and platinum wire. We are eager to partner with customers in the areas of thermosonic flip chip bonding, using the gold-gold interface. As far as wedge bonding into advanced packages with limited space requirements, we have had success with our 89° bondhead, and also the S-shaped bonding capabilities of our thin and heavy wire bonder. A lot of our customers are requesting higher-speed capabilities on the wedge bonders.

Paul Raymond, VP/General Manager

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Honeywell Electronic Materials,
An economic atmosphere like this means that suppliers, such as Honeywell, must be sure to demonstrate the competitive value of their products. In 2004, we took a number of steps in this direction, including expanding through acquisition our leading edge thermal solutions for packaging and buying our joint venture partner in GEM Microelectronics. We plan to expand our offerings in wet chemistries and to offer performance cleans, ultra-high selective etchants and wafer-thinning products designed to meet specific customer needs.

In 2005, we plan to focus on unique advance lithography antireflective coatings, application-specific chemical etchants, 300-mm copper alloy PVD targets, and sapphire substrates for blue LEDs. The diversification of our product portfolio is a key piece of our business plan. The cyclical nature of our industry is unlikely to go away. It is incumbent on Honeywell and all participants to seek the opportunities based on value and innovation to ensure that the longer-term trend continues to be one of rapid growth.

As we head into 2005, the predicted industry downturn is on the minds of all companies in the semiconductor industry. However, most indications are that any downturn will be much less severe and shorter than the last shock. Clearly, the semiconductor industry’s challenges include the maturing of the desktop market as well as the flooding of the hand-held market, which has yet to provide a winner. The creation of standards in the mobile computing marketplace remains an issue that needs to be resolved.

Fritz Byle, Senior Advanced Products Engineer

Kester has exceptional flexibility in addressing the dynamic electronic materials marketplace. Our product line will undergo significant evolution in 2005, with an increased focus on products designed to improve economics and reliability of lead-free packaging, new and unique thermal interface products, and enhanced products for lead-free assembly.

The impending transition to lead-free is poised to have a major impact on packaging in 2005, with only a year to go until the EU RoHS initiative kicks in. For flip chip-based packages, this will be complicated by the introduction of low-k semiconductor dielectric materials. This combination is sure to challenge existing packaging material sets and create new opportunities for innovative ideas in packaging technology. Flip chip on flex (FCoF) is poised for take-off as an enabling technology.

Peter Bierhuis, President

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March Plasma Systems,
With general industry forecasts depressed for 2005 and capacity buying expected to be at reduced levels, we will continue to emphasize applications and product development for the newer packaging technologies. Growth rates in flip chip, QFN, stacked die, and advanced substrates continue to outpace the general industry with positive implications for the use of plasma processes. We will continue on our path of expanding our local capabilities in the Asia Pacific region to support our customers’ growing local presence. Following the establishment of our Japan and Singapore operations, we will set up a direct operation in China in early 2005.

Joel McGrath, Director of IC Packaging Development, Systems Design Division

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Mentor Graphics,
Mentor Graphics is making a significant investment in the development of next-generation IC packaging tools that will meet the design challenges facing our customers today and in the future. Advances in IC and IC packaging technology are putting tremendous pressure on package designers with added complexity and performance requirements; while, at the same time, are being challenged to reduce packaging cost and time-to-market. Delivering a flow-based design methodology that can streamline the design process will be critical.

With advances in system-in-package (SiP) technology coming at such a rapid rate, we see a significant challenge in developing design tools and methodologies that will enable designers to create optimized designs that can meet the required performance and cost targets. On a single substrate, you can find stacked and side-by-side die configurations, mixed RF and digital circuitry, as well as buried actives and passives. Current design methodologies and tools do not do a good job at supporting these design challenges. We are developing tools and methodologies that specifically target these new challenges to deliver a integrated design flow.

Bruce W. Hueners, VP of Marketing

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Palomar Technologies,
We have new products in the queue aimed at emerging applications that require high-precision positioning, clean processes, high thermal dissipation, high current carrying capacity, and competitive cost of ownership. Some of these applications include laser diodes and RF devices that require high, accurate placement, coupled with efficient heat dissipation. An emerging application is the CMOS sensor used in higher-resolution cameras for cell phones. We are also leveraging our process development expertise in multichip packaging to address the latest designs and trends in interconnect technology.

One of the most difficult challenges will be to develop equipment that can handle the increasingly high thermal output of new devices, be able to deal with smaller parts with micron-level accuracy and precision, and still keep cost of ownership low enough for the manufacturer to be profitable. Another industry challenge will be converting to lead-free. We use gold wire to make bumps for a gold-to-gold interconnect, so we have a ready-made alternative for lead-free attach.

David Pfaff, COO

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We see the continued decline of U.S.-based manufacturing, design, and development. Factories in Asia are becoming more efficient and more and more of our customers’ decision making and development work are taking place in Asia. In that regard, Plastronics is allocating more capital and more resources in expansion into SE Asia than in previous years. The skill sets of molding, tooling, and stamping vendors in China will be equivalent or better than U.S. and Japanese skills by the end of 2005, and the cost structure will remain vastly lower.

The challenges are more of the same, with regards to test and burn-in connectors: tighter package pitches down to 0.3 mm; larger BGA and LGA grid sizes up to 2,700+ pins with increased warpage; higher current requirements in terms of amperage that contacts need to carry; higher frequency requirements; and heat dissipation from the packages. The need for new materials and new molding processes to meet these requirements is becoming increasingly more difficult to source. The greatest challenge in the past 3 years, and going into 2005 and the next few years, will be heat dissipation and the need for a full system solution that works across multiple platforms. Although solutions are available, they are expensive and customized for each requirement.

Diane Cox, VP, COO

Royce Instruments Inc.,
Royce Instruments Inc. has always thrived on being able to take on the new challenges our customers ask us to meet. In 2005, we are expecting to make strong progress on many fronts, including both our bond-test and die-handling product lines. We are making many improvements to our production and customer support processes that will enable us to meet our customers’ needs. We are expanding our global presence by strengthening our network of sales partners, both internationally and in the U.S. We are continuing to see an increase in our particular market niche of low-volume R&D and prototype die-handling systems, which we expect to continue into 2005.

Among the challenges we are facing in advanced packaging is providing solutions that are flexible enough to handle an increasingly wide variety of applications. We are seeing bond pitches decrease, both in wire bond and flip chip packages, and this requires precise tooling that is robust and reliable.

Kurt Lackenbucher, Executive VP, COO

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SEZ Group,
Semiconductor packaging has typically been considered a lower-end market for cleaning applications because the requirements are less stringent than for device manufacturing. However, we see considerable growth potential here, as well as in silicon-substrate manufacturing and other applications still focused primarily in the 200-mm wafer arena. This allows us to leverage our existing 200-mm tools, optimizing them to extend the reach of single-wafer technology beyond the fab line. We are just beginning to penetrate the packaging business; in 2004, we sold our first under bump metallization (UBM) etch tools to a major Taiwanese player, and expect to see greater demand in this sector. Our UBM-etch solution is our second foray into the advanced-packaging sector, the first being our substrate-etch technology for wafer thinning, surface conditioning, and stress relief on high-performance IC packages. The next beyond-the-fab area we see a need emerging is photoresist stripping and cleaning.

In 2005, we do not see specific technology challenges emerging in the packaging sector; the challenge is cost. While single-wafer technology typically targets 300-mm wafers and 90-nm and smaller geometries, in our view, you can achieve better results on single-wafer tools for less cutting-edge requirements as well. For example, one of the major issues in packaging is handling - avoiding breakage and mechanical damage on costly, finished wafers is vital. This is a strong advantage for single-wafer technology, where the chance of damage is minimal compared to batch processing.

Joseph Fjelstad, Founder

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SiliconPipe Inc.,
2005 promises to be a landmark year in which copper interconnection technology is re-established as a solution for high-speed applications. At SiliconPipe, we expect to see increasing numbers of the innovative concepts that the company has been working on for the last 3 years taking on physical form, beginning with the Advanced Packaging Award-winning OTT package. These and other structures will be finding their way into advanced electronic products and applications that can benefit from the performance boost that the innovative technologies provide. Backplane switches, routers, video, and memory products lead the list of first beneficiaries, but there are many that will likely follow.

The introduction of new technologies into the electronics industry is always a difficult challenge, even when they provide significant cost and performance benefits. Overcoming the inertia of the status quo requires substantial effort because change, of any sort, is nearly always the bane of manufacturing. Still, as new ideas are proven and take root in the minds of the product development community, it will be their force of action that will drive the flywheel of manufacturing. In most cases, the benefits of viable new technologies will be realized, first by early adopters and then by close followers.

Pierre de Villemejane, President, CEO

Speedline Technologies,
We have invested heavily in R&D for our products for the packaging industry. This investment has resulted in many new and exciting platforms that will bring new standards of performance to the industry. Dispensing applications continue to be a strong focus for us in 2005. Many new developments will be launched as a result of our applications efforts with flat panel display, hard disk drive, and cell phone manufacturers.

As consumers continue to demand smaller portable electronics with increased functionality, the trend toward shrinking form factors will continue in 2005. With the increased usage of small-pitch, high I/O devices, it is even more important to control bridge defects. Inspection processes are critical. The spacing between die and passive components also is shrinking, and underfill applications continue to increase. The accuracy of X/Y dispensing systems must increase to reliably dispense material into these tight gaps. The transition to lead-free manufacturing will continue throughout 2005. There has been much effort over the past year to establish lead-free solutions and processes. The challenge will be to implement these new processes in manufacturing facilities across the world. As a supplier of reflow and wave soldering equipment, we are prepared for this transition and can provide assistance to our global customer base.

Tan Lay Koon, President, CEO

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STATS ChipPAC is focused on leveraging our leadership position in 3-D packaging and mixed-signal test technology to provide our customers with turnkey solutions to bring their advanced products to market faster. As consumer, computing, and communications end products become smaller and more feature-rich, having the right packaging and test technology at the right cost becomes increasingly important. Our merger last year has given us the most balanced turnkey service offering in the industry. With a broad geographic footprint and deep pool of technology resources, we are rapidly increasing the breadth of services that we supply to our customers. In 2005, we expect to expand production of stacked die, stacked package, and flip chip interconnect. We also plan to continue investing in newer-generation mixed-signal and digital-test platforms to support turnkey manufacturing. We see an increasing opportunity for our company to better serve our customers by taking a more active role in managing the upstream supply chain. We expect to roll out a variety of supply chain services in 2005, tailored to our individual customers’ needs.

The volatility of the semiconductor market continues to be a challenge. Our industry has not been particularly efficient at predicting what is increasingly becoming consumer-driven demand and installing the appropriate amount of production capacity. This creates frequent disconnects throughout the supply chain with alternately constrained and excess supply. The second half of 2004 saw inventory buildup in some semiconductor market segments. We are optimistic that with reasonable end-market pull-through during the end-of-year season, the industry can look forward to moderate growth in 2005.

David Haynes, Director of Sales & Marketing

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Surface Technology Systems,
In 2005, STS will continue to develop manufacturing processes for advanced packaging concepts. Key drivers for our development plans are etch rate, profile control, uniformity of processing, and wafer throughput. As the device manufacturing process becomes more efficient, packaging is increasingly seen as a major overhead, and any technology advances that reduce packaging costs add benefit to the end user.

In advanced packaging, the diversity of applications of chip scale techniques, including flex interposer, rigid interposer, leadframe-based, and wafer level results in a broad range of process requirements. 3-D interconnect strategies, including system-in-package (SiP), add additional complexity to the range of process options. The range of variables includes wafer size; substrate material (Si, glass, quartz, Pyrex, and fused silica); the thickness of substrate and its impact on flexural rigidity; and also specific device constraints, e.g. silicon thickness, bond pad pitch, street width, via dimensions, and a metallization scheme.

Craig Mitchell, VP of Marketing

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Tessera Inc.,
Tessera will continue to develop new technologies and services that enable electronics integration and miniaturization across key markets, including the wireless/portable, digital consumer, computing, medical, and military/defense industries. Specifically, a key area of focus for us will be on system-level design issues. To realize the promise of system-level design, a fundamental shift in the design community’s thinking is required. A new design methodology is needed, one that defines the optimal miniaturization path of an electronic product from the outset of product design. One such methodology is called system-level integration and miniaturization (SLIM). This new design methodology is multidisciplinary in nature and spans a product’s development cycle, including device, package, module, and system level design; electrical, thermal and mechanical analysis, and characterization; and component selection, product assembly, and test. The cornerstone of the SLIM approach is advanced electronics packaging, specifically system-in-package (SiP) technologies. SiPs are critical to the SLIM methodology because of their inherent ability to integrate heterogeneous technologies, minimize footprint, and reduce product development cycles at the lowest possible cost.

Alan Strassman, Advanced Packaging Engineering Manager

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Tyco Electronics,
While we continue development to capitalize on and exploit the many advantages of our flexible advanced packaging offering, Tyco has been able to create a synergy of equipment and in-house process expertise to produce a very competitive, flexible, reel-to-reel RFID tag assembly line. This line features our hybrid die bonder, allowing direct pick of flip chips from wafers, which eliminates the need for straps and provides substantial cost savings. The massive growth potential of this industry provides exciting opportunities.

Richard Boulanger, VP

Universal Instruments,
We intend to become the lowest-cost, total solution provider in the industry, and 2005 is the year we expect to make dramatic progress toward this goal. There are four major components to this: robust and flexible technology, as evidenced by our ‘platform’ concept, which will continue to attract substantial R&D investment; an aggressive cost containment strategy that demands continued globalization; intrinsic equipment availability where and when customers need it; and a fair, long-term attitude to pricing with a global perspective. On the advanced packaging front, we will introduce a substantially lower-priced linear motor machine. We are continually improving our wafer feeder capabilities and our vision offerings.

New applications like stacked dies, embedded components, RFID and LEDs are coming of age. Smaller (0.25-mm) and thinner (50-µm) dies are becoming the mainstream. Components are getting smaller (0201 and 01005) and larger (22-mm2 flip chip dies with more than 8000 I/Os), thus stretching our flexibility capabilities.

Vikram Butani, President

VJ Electronix,
As component sizes get smaller, the challenge to provide better test and inspection tools becomes critical to the R&D and FA processes. X-ray inspection using 3-D computer tomography provides information not available with any other tool. This method has not been very popular in the past due to the image acquisition time and system cost restrictions. The need to obtain a better 3-D x-ray tool is imperative, and we believe this will be a critical challenge for the semiconductor industry.

We have been providing true 3-D x-ray inspection systems for a few years. This year, we are ready to introduce an inspection system that will provide images at speeds far greater than those provided by any other system in the industry. Acquiring data at almost real-time speeds will speed up the R&D and FA processes, thereby reducing time-to-market for the semiconductor industry.