Issue



3-D Design of Stacked Die and SiP


01/01/2005







MEETING REQUIREMENTS OF COMPLEX PACKAGING TECHNOLOGIES

BY GORDON JENSEN

As stacked die, system-in-package (SiP), and chip scale packaging become the defacto standard in the ever-shrinking world of electronic systems design, complex bond wire and other 3-D clearance issues are becoming increasingly critical in the design and manufacturing process. Traditional 2-D package design tools cannot take into consideration wire bond clearances and die placement tolerances inherent in the manufacturing process, which results in increased trial and error and poor yields as package complexity increases. By using intelligent tools that perform 3-D design rule checks (DRC) and placement tolerance simulations, bond wire stacked die designs can be optimized for improved yields and reduced manufacturing set-up times.

The market for stacked die, stacked packages, SiPs, chip scale packages (CSPs), etc. has grown steadily in the continual quest for smaller portable and wireless applications. These package types dramatically reduce real estate on the system board, and also expand functionality in a single package. While the system-on-chip (SoC) market also is expanding, successful implementation of SoC requires substantial development time and resources, as well as high set-up costs. SoC packaging, therefore, is geared toward high volume, where economies of scale can reduce the final cost of each IC. In contrast, stacked die, multichip modules, and SiP technologies use various combinations of existing manufacturing technologies and infrastructures, can combine ICs of dissimilar materials and processes to be implemented in a system design rapidly - substantially improving time-to-market.

Traditional packaging layout or design of leadframe, single-die BGA and other packaging types has been accomplished using a 2-D layout environment. The single- layer die pad configuration, conventional 2-D layout tools coupled with 2-D DRCs have been adequate to produce a package with relatively high manufacturing yield.

In a traditional 2-D package, layout is accomplished using in-line and post-layout DRCs that ensure the package layout conforms to existing 2-D manufacturing technology. The design rules generally are straightforward, since only a top view is considered.

During the manufacturing process, these types of 2-D packages are easily inspected using traditional 2-D x-ray systems. Clearances are easily checked and verified during the set-up and manufacturing process, and the combination of these 2-D layout and manufacturing inspection techniques are sufficient to ensure good yield of the package.

As the IC’s I/O count increases, more complex substrate and die bond pad configurations must be used. Designs such as ICs with a staggered pad layout are more difficult to complete with conventional 2-D software. It is more difficult to confirm manufacturing yields using only top-down inspection tools. These designs, however, are still possible in a 2-D environment.

The complex 3-D design environment of stacked die, SiP, etc. cannot be translated into a 2-D layout system. 2-D DRC rules do not take into consideration heights and other clearance issues that are inherent in the manufacturing process. Thus, a major portion of required 3-D DRCs are not possible, which leaves the process of design verification to the manufacturing side.


Figure 1. 2-D x-ray inspection of a stacked die package.
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Manufacturing, therefore, is faced with the task of creating bond wire profiles with sufficient clearances. Although an experienced bond wire machine operator can reduce the amount of time involved in creating wire bonds that meet manufacturing tolerances and clearances, it essentially is still a time-consuming trial and error process. Typical 2-D x-ray inspection systems are not able to distinguish elevations or 3-D features, and are not viable inspection systems for these types of packages (Figure 1).

The end result is a repeating cycle in which the manufacturing engineer creates a wire bond package and a sample, locates errors, makes adjustments, and goes through the cycle over and over. If the errors are not correctable at some point by the manufacturing engineer, the design must be sent back to the design engineer for a redesign of the substrate, further lengthening time-to-market and costs.

3-D Design Process Breaks Re-engineering Cycles

To accurately verify complex SiP and other multichip packages, 3-D design rules and verification must be incorporated into the design process flow (Figure 2). By using 3-D design in the package layout process, proper 3-D manufacturing tolerances are verified in the design process, and correct data is sent to manufacturing. This eliminates costly trial and error and redesigns.


Figure 2. Design flow with 3-D package design tools.
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Typical 2-D package design flow consists of die placement and pad layout. This is followed by the substrate design or layout and, after final 2-D DRC, the data is output in the form of Gerber or other data formats for fabrication and assembly.

The basic design flow using 3-D tools follows the same general conventional 2-D layout process. However, after substrate bond pad layout is completed, and before substrate layout and routing is performed, the additional 3-D verification tools are used. First, bond wire profile data is created or input into the 3-D system. These 3-D wire profiles are assigned to each wire location, and wire diameter and other parameters are also entered. Die placement tolerance for each stacked die is entered as X shift, Y shift, and theta degree shift tolerances. These placement tolerances can be referenced either to the die below each die or to the substrate.

A 3-D model is then generated, and clearance checks based on the maximum placement tolerances (X, Y, theta) are automatically performed. Each location that is below set clearance minimum is automatically highlighted graphically at the minimum clearance location, and includes pin and wire locations, measured clearances, etc.


Figure 3. 3-D capillary design tool.
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Clearances may also be checked between capillaries and wires. Capillary dimensions may be input or designed in a 3-D capillary design tool (Figure 3). Once the capillary data is input or a capillary has been designed, the 3-D system performs automatic capillary-to-bond wire clearance checks. If there is a capillary-to-bond wire clearance violation, the location is identified and adjustments can be made (such as changing bond wire profile parameters, etc.). An automatic wire sequencing order can also be created that optimizes capillary sequencing. This results in the creation of a complex bonding diagram that can include any combination of ball bonding, wedge bonding, reverse-ball bonding, etc., with no capillary-to-wire clearance errors.

Capillary-to-bond Wire Clearance Error

Once all of the 3-D design checks have been completed and one or more clearance errors have been detected (wire-to-wire, wire-to-capillary, wire-to-die, etc.), several options exist for eliminating these clearance violations, thereby increasing manufacturing yield during the design process.

If the 3-D verification is done prior to the layout
outing of the substrate, substrate design modifications are possible. A closer look at the substrate bond pad pattern and location may reveal potential sources of clearance violations that can be improved by modifying the pad pattern or location.

In addition to substrate bond pad changes, bond wires can also be modified to increase clearance. Various wire profile parameters can be changed. In addition, different bond wire profiles may be selected for a particular wire or set of wires to increase clearances. Further, bonding sequence can be modified in order to provide sufficient capillary clearance.

At any time during or after any (or all) clearance modifications have been done to the substrate pad locations or to the bond wires, 3-D design checks can be re-run to verify that the changes result in sufficient clearance for manufacturing and assembly. This optimized design is now ready for substrate routing, or if already completed, the data can be output to manufacturing for substantially reduced set-up time.

This 3-D design verification process is ideally suited for determining the realistic manufacturing feasibility of a specific die and substrate. Using automatic die placement and substrate bond pad fan-out creation, wire bond and capillary parameters can be entered into the tool, and the die/substrate/wire bond package can be evaluated for manufacturing feasibility - prior to investing substantial resources in substrate layout. This aids the package assembler in the quotation process, since feasibility of a particular die and substrate package can quickly be determined prior to quotation submission. Mismatched packages can be corrected with the customer during this initial quotation process, substantially reducing wasted effort on non-manufacturable die-substrate mixes.

Case Study

A two-level, stacked die SiP was originally designed using a conventional 2-D layout system. The package consisted of three chips; a lower memory chip, with a logic chip and terminal chip mounted on top of the memory chip. The completed SiP design was sent to fabrication, and the package was subsequently assembled. Upon test, however, the product exhibited a low yield rate because of internal shorting, and manufacturing was stopped.


Figure 4. Two-level, three-chip SiP, nominal placement tolerances.
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Through further inspection of the package, it was determined that there was a reoccurring short between two specific pins in a high percentage of the packages. To determine the manufacturability of this specific die/substrate package, the package was subsequently redesigned using 3-D design flow methodology as listed above. After the dies were created and placed, the substrate bond pad pattern was created. Then, bond wire profile data and all die placement tolerance data were input into the system. A 3-D CAD model was generated, and an automatic clearance check of all bond wires at all maximum die placement tolerances was performed (Figure 4).

The result of clearance checks revealed a short between two adjacent wires that occurred within die placement tolerances. In this instance, a short occurred on one wire pair at three different placement tolerance extremes (+X, -X, and -Z). The 3-D DRC results also showed that there were no other shorts observed in any other wire combination at any other placement tolerances maximums.

Further mechanical inspection of the defective part revealed a short at the specific bond wire location as identified in the 3-D evaluation of the package design, and this data corresponded with the initial inspection results of the package during manufacturing test. The integrated 3-D verification system was able to accurately predict the specific location of the error, allowing the design engineer to modify the design to improve manufacturing yield.

3-D Manufacturing Feedback System

A complete 3-D design system will ideally integrate design and manufacturing functions to produce higher yields and faster time to market. Not only must bond wire and capillary clearances be checked during the design process, but actual manufacturing data should ideally be fed back into the design process to more accurately optimize the package design. This feedback process is accomplished through specialized manufacturing data extraction. A special x-ray system is used to capture multiple angle images of the bond wires in the molded package. The images are then processed through special 3-D conversion software, and the wire bond images are vectorized to automatically create 3-D manufacturing wire bond data.

This process allows designers to recreate 3-D-manufactured bond wire data from manufacturing data. By creating this actual 3-D manufacturing data and inserting it into the package design, all 3-D clearance checks, etc. can be performed on the actual manufacturing bond wire data. Subsequent adjustments to wire profiles, etc. also can be done to further optimize the package.

With actual manufacturing data now in the design, the design department is now able to better simulate manufacturing variations and tolerances, and work closely with the manufacturing department to improve yields.

Conclusion

Complex SiP package design requires advanced 3-D design capabilities that are beyond the capability of conventional 2-D design and layout tools. Conventional 2-D design flow consists of die placement and pad layout, substrate layout and routing, and Gerber output for top-down manufacturing. These traditional 2-D software tools cannot incorporate 3-D manufacturing requirements or verification, making it impossible to take the guesswork and trial and error out of manufacturing and assembly.


Figure 5. A complete 3-D design/manufacturing system.
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As SiP and other advanced packages become increasingly more dense and complex, a separation between the design and manufacturing/assembly processes is not a viable model for increased yield and faster time-to-market. A solid integration between design and manufacturing/assembly is necessary to overcome the difficult challenges placed on both package design and package manufacturing/assembly with these new packaging technologies.


An ideal SiP design solution will incorporate all functions of traditional 2-D design, as well as full 3-D design and manufacturing verification, expanded data output to manufacturing and assembly (wire bonders, pick-and-place, etc.), and incorporate CAD data feedback from manufacturing back into the SiP design for true design-for-manufacture (Figure 5). These new 3-D systems will enable design and manufacturing to jointly meet the requirements of increasing complex packaging technologies.

Editor’s Note: This article was originally presented at the International Wafer-level Packaging Congress, San Jose, CA, October 10-12, 2004.

GORDON JENSEN, president, may be contacted at CAD Design Software, 15055 Los Gatos Blvd., Suite 300, Los Gatos, CA 95032; (408) 358-3305; e-mail: gjensen@cad-design.com.