Issue



Design Considerations


01/01/2005







Wafer-level CSP RDL

BY DAVID SEMPEK

The wireless handset industry is growing at a tremendous rate. Included in this growth is the demand for consumer products with higher bandwidths for e-mail, faster data downloads, games, short message services (SMS), JPEG files, Java applets, ring tones, and so on. Meeting these demands requires high-speed memory ICs, such as low-power or mobile DRAM, PSRAM, and flash NOR or NAND memory. These memory ICs can handle the data bandwidth read-and-write times and are more “battery friendly” than conventional memory. In addition to memory requirements, with 3G and Smart phones, for example, handset suppliers add an application processor for PDA functions.

The cell phone handset is just one example of major consumer trends for electronics products in many market areas that are smarter, lighter, faster, and full featured. With these advances in technology, consumers also are looking for products with higher reliability, less expensive unit cost, higher data performance, and ease of use. Each increase in demand also increases the need for higher in-system clock frequency in the associated electronic components.

With clock speeds for digital circuitry continually increasing, one concern is how to handle signals from a semiconductor device to the associated PCB, and what type of interconnect should be used. Device interconnects or bonds can either enhance or degrade high clock speeds; bond lengths need to be as short as possible to maintain high signal integrity. Device standby and active currents also must be considered. System designers are limited to a power consumption budget. For example, bonding dielectric materials that have relatively high dissipation factors can contribute to power loss. Overall, any losses in power due to bonding interconnections that cuts into a given “power budget” can be very costly, ultimately limiting the time a wireless handheld unit is not in its charger.

The Manufacturing Challenge

Consumer product trends and solutions to system power issues put pressures on IC fabrication. This situation is further complicated by the fact that the associated ICs are also going through normal design shrinks; package design engineers must constantly address better, more cost-effective solutions.

Redistribution layer (RDL) technology is applicable for ICs that have a limit in bond pad location, where a change to that limit can alleviate power loss. ICs in power-crucial consumer applications that can benefit from RDL include micro-controllers, digital baseband (DBB) chips, EPROMs, flash, etc.

RDL can rearrange bond pads to any location (within reason) on a die. With RDL, for example, an IC with bond pads that conventionally run through the center of the die can be redistributed to the periphery of the die, to both sides or to just one side. With such changes, one advantage to the redistribution is that system and package designers can consider more flexibility in die distribution scenarios for system-in-packages (SiPs), such as die stacking, “shingle” stacking, or stacking with side-by-side placement.

RDL with flip chip technology is gaining popularity for stacking dies in a single package because most of the in-demand consumer electronics products have limited PCB real estate; the principle example is a cell phone handset. Stacking dies, or stacking packages, allows for more feature-rich, competitive designs that may include CMOS image sensors, MP-3 players, and video streaming.


Figure 1. I/O resistribution on a low-power DRAM. Courtesy of Micron.
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DRAM Example. Consider DRAM ICs. For voice and data-centric cell phones, handset designers are beginning to use low-power DRAM devices because of inherent in-system performance read-write access time advantages, along with power friendliness. To achieve additional bandwidth, designers are stacking low-power DRAM. These DRAM die, however, are not easily stacked because their conventional JEDEC bond pin-out configuration is down the center and across each end. This conforms to sense amplifiers and other circuitry that run through the center of the main memory array. RDL can be used to reroute conventional bond pads of low-power DRAM to alternative locations for flip chip applications (Figure 1).

RDL Options

RDL fabrication technology includes well characterized metallization options: single-level aluminum (Al), and single- or multi-level copper (Cu). Al has proven adequate for many designs, but Cu is a better conductor.

Multiple Cu levels are possible with ≥3-µm thicknesses; thicker Cu has higher current carrying capabilities. Guidelines for high-volume manufacturing that allow for 12-µm trace widths and ~13-µm spacing results in good process control and yields. Improvements to these dimensions up to 10 µm are possible, but process capability, reliability, and manufacturability need to be reviewed. Multilayer thin film (MLTF) RDL is another option that allows as many as 4 layers of fan-in and redistribution, which is leading-edge for copper metallization plus solder wafer bumping.


Figure 2. a) An inductor fabricated with MLTF RDL technology, and b) a cross section of multilevel wiring. Courtesy of Unitive.
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A multilayer metallization scheme allows designers to route device signals plus the power and ground planes, as well as adding integrate passive components such as resistors, inductors and low-value capacitors (Figure 2). Line-space dimensions with aspect ratios of 6:10:6 or 10:10:10 are an important consideration with passives.

RDL Characteristics


Figure 3. BCB dielectric constant and dissipation factor.
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When applying RDL, engineers must consider that different designs may have different materials properties that can limit device signal integrity and change manufacturability. Materials properties, for example, can significantly affect an interconnect’s capacitance, which can change signal integrity so much that the device will not be properly terminated. Here, we have used modeling to review bond dielectric constants as a function of frequency. Our engineers found empirically that frequency response does not change as frequency is increased to 10 GHz. With poorly designed interconnects (e.g., marginal dielectric properties), however, the overall frequency response could drop if capacitance is too high. Given a specific materials property configuration, we used software* to calculate the inductance and capacitance of materials using a boundary element method with multi-pole acceleration. In this case, benzocyclobutene (BCB) was analyzed specifically, reviewing the dielectric constant and dissipation factor as a function of frequency. The data show that there was no degradation to the applied frequency when ramped to as high as 10 GHz (Figure 3).

RDL mechanical characteristics relate to board-level reliability (BLR) and are dependent on die size. For example, a 7 × 7-mm die is capable of 500 -40 to +125°C thermal cycles (IPC-9701 TC1) or 3,000 0 to +100°C thermal cycles (IPC-9701 TC3), without underfill. If the application demands a TC1 temperature profile, the engineer can use underfill to address the stress of the thermal cycle and improve BLR. When underfill is not a viable option, the application may call for flip chip BGA or another appropriate package.

With RDL, the principle current path is through the top of the die, then through the bump; typically 80% of the thermal performance is at the bump contact. Proper design of interconnecting bumps to the substrate is required for successful thermal management. To ensure that interconnects can dissipate power from the die, the width and length of the metal distribution must support the die’s total current and frequencies.

Correctly applied, RDL can improve the thermal performance of an IC, reduce impedance, and limit the inductance that would be expected with a typical TSOP or other semiconductor package; this is done through design of trace lengths and selection of materials.

Cost and Performance

The application of wafer-level CSP RDL requires a careful analysis of cost trade-offs. While using Cu RDL with bumping may seem more costly from the materials point of view, cost advantages come from processing all die on the wafer at one time compared to processing single die or strips of die, as is done in conventional assembly and packaging. In addition, RDL potentially reduces the number of layers on a laminate substrate; if this is properly applied to avoid reliability issues, it can result in a significant cost advantage while providing better overall signal integrity.

An additional cost advantage to RDL is the life expectancy of legacy designs can be more cost effectively extended through the use of RDL in lieu of costly silicon redesign. Minimal non-reoccurring engineering costs are generally associated with RDL vs. complete mask sets needed for silicon redesign.

* Ansoft Maxwell Q3D Extractor.

DAVID SEMPEK, director of advanced product development, may be contacted at Amkor Technology, 1900 S. Price Rd., Chandler, AZ 85248; e-mail: dsemp@amkor.com.