Microelectronics Design and Manufacturing
Then and Now
BY DAVID WIENS, Mentor Graphics Corp.
The more things change, the more they stay the same. Microelectronics design and manufacturing technologies have made huge strides, yet many of the technology and business dynamics that held true in the ’70s and ’80s are still accurate today.
Table 1. Then/Now markets/drivers/terminology and challenges.
In those days, size and weight were primary drivers, but reliability and stability were also highly prized. The predominant market for these devices was the military/aerospace domain where RF applications took advantage of the technology’s unique ability to combine analog, digital, and RF circuitry within a small package (Table 1).
Microelectronic circuits saved size by eliminating packaging around active devices, burying passive devices inside the interconnect structure, and using technology borrowed from IC fabrication to reduce the size of a circuit’s interconnect. Commonly known as hybrids, they used technology from both monolithic silicon ICs and the discretely packaged world of PCBs, and were created using either thick- or thin-film technologies. In the late ‘80s, multi-chip modules (MCMs) emerged, driven primarily by performance constraints for digital applications.
The reliability of microelectronics products increased by reducing the number of physical connections to discrete devices, and packaging the complete circuit within a hermetically sealed container. The resulting structure suffered minimal damage from shock and vibration, further increasing its reliability. Microelectronics performed better than their PCB counterparts due to improved signal integrity and RF performance/stability. Additionally, they were more testable, and cooler (thermally and visually).
Similarly, hybrids had significantly lower non-recurring expenses (NREs), making them more appropriate for low-volume applications. Their hybrid ability to support active and digital circuits within tight tolerances made them suitable for mixed-signal applications.
Impact on the Design Process
Hybrids introduced integrated passives, which meant that standard footprint libraries could no longer be used; device geometries depended on the properties of materials used in the layer stack-up. Designers had to be more aware of material properties because that drove passive component synthesis - parameter-driven automatic creation of device geometries - as well as heat dissipation potential. Active devices also created a design twist. Because they were unpackaged, designers had to deal with bare dice that were wire bonded from the top with unique and flexible bond pad patterns, or were flipped, with land pads created across the entire surface - not just on the periphery - of the device.
Figure 1. Cross-over trace created with localized dielectric.
Depending on the chosen fabrication technology, interconnecting vias had a unique set of constraints for staggered or stacked patterns. Traces were often similar to PCBs; however, thick-film hybrids used localized dielectric, enabling designers to save costs by using only as much inter-layer isolation material as necessary. Designers that were used to having a full layer available for interconnect had to be careful to avoid routing a trace into space, effectively creating a short with the layer underneath (Figure 1).
Finally, once a design was verified for manufacturability, it was time for manufacturing output generation. Now, artwork had to be generated for conductive, dielectric, and resistive masks to account for integrated passives, localized dielectric shielding and via filling. Data for wire bonding also had to be generated, including from/to layers, since ICs were often inset in cavities. The design of microelectronics was more complex than traditional PCB design, so design tools for hybrids and MCMs tended to be super-sets of PCB tools.
Today’s Applications for Microelectronics
The drive for ever-decreasing form factors is created by the desire to integrate an ever-increasing number of previously discrete products/functions into one device. To accomplish this task, different manufacturing process technologies must be integrated.
Today, instead of monolithic ICs, people talk about system-on-chip (SoC), and rather than thick-/thin-film hybrid circuits, engineers talk about systems-in-package (SiP). SoC enables the highest-possible density-per-function, but also comes with the highest NRE. SiP enables high densities - not as high as SoC, but much higher than PCB. It accomplishes this by integrating some components within the substrate (now known as embedded passives), while keeping unpackaged ICs in discrete (non-integrated) form within close proximity of each other. Designers pushing the envelope even embed active devices within a substrate, but these are not integrated (i.e., they’re still fabricated separately, then inserted into the substrate). The resulting SiP is more flexible and less expensive than SoC because existing functional “blocks” in the form of discrete chip sets can be re-used; they don’t have to be engineered and fabricated into the core structure. This is particularly true where mixed analog, digital, and RF technologies are to be integrated. It is much easier to design these as discrete, optimized blocks than to integrate them all within a single device.
Some people claim that SoC will eclipse the other electronics design disciplines, SiP and PCB included. But, arguments in favor of SiP have made it a viable alternative for systems designers, ensuring its place in the electronics food chain.
The increasing functional complexity of modern products has required an equivalent increase in passive devices, primarily in the form of decoupling capacitors and terminating resistors for low-power, high-frequency applications. While surface mount device (SMD) packages for passives have shrunk considerably over the years, the answer is still the same when trying to achieve maximum density - bury them. Printed components made the transition from MCMs and hybrids to today’s SiPs and PCBs as embedded passives. Along the way they’ve been adapted to current fabrication techniques. For example, the inclusion of a resistive material layer within a core laminate structure, and the creation of series termination resistors directly underneath micro-ball grid array (μBGA) packages, have improved circuit performance. Embedded passives can now be designed with tight enough tolerances to avoid the extra manufacturing step of laser trimming. Wireless components are also seeing increased integration within the substrate.
Design tools have had to evolve to support the different embedded manufacturing technologies. Design solutions that can handle materials libraries, and use the specific device parameters to synthesize design-specific geometries for embedded passive and RF elements, are critical.
IC Mounting and Pin Attach
Eliminating IC packaging and working with bare die was the first-level size reduction technique that is still used with two predominant bonding methods: wire bonding and flip chip. An even higher level of density has been achieved recently by stacking die on top of each other and connecting them directly to each other or to the substrate via flip chip or wire bonding. This has required designers to work within three dimensions to efficiently connect the wires without shorting them together, and produce instructions so that automated wire bonders don’t destroy one wire while bonding another.
Yesterday’s thick- or thin-film-enabled blind/buried vias are today’s microvias within a high-density interconnect (HDI) structure. In many cases, HDI is the only option available to interconnect fine-pitch, high-pin-count devices to the substrate.
Working with HDI has caused designers to deal with new via structures in addition to the typical holes through the laminate core. Designers have adapted to blind/buried via structures, but the new HDI structures add even more complexity.
Figure 2. Multiple die stacking enables higher circuit density and electrical performance.
Signal speeds on SiP already exceed the speeds achieved on SoC, making it faster to integrate between discrete devices than within a chip. Optoelectronics are also now entering the fray, promising even higher performance with minimal signal distortion, all in even smaller geometries.
System Design and Verification
Today’s electronic systems have a more complex silicon-package-board interface than traditional devices. Unfortunately, design methodologies result in a segregated “black box” design relationship between each physical design element, making coordinated planning a difficult and non-optimized task.
This has inspired a new generation of design solutions in the areas of system-level design definition/partitioning, I/O mapping, and verification. The resulting process improvements have enabled shortened design cycle times and increased product performance. They have also enabled trade-offs between the high-cost, high-NRE world of integrated silicon SoC and multi-chip SiP or PCB options. In the future, many technologies will develop in both environments simultaneously, due to the increased similarities in fabrication that have developed over time, and the continued drive to design complete systems.
As IC, packaging, and PCB design and manufacturing technologies have evolved, intrepid designers have found ways to leverage technology from one discipline to another so that all three forms of electronics share common advanced fabrication methodologies. The development of a manufacturing infrastructure that could cost-effectively produce these advanced technologies on a SiP or PCB has been their primary facilitator, enabling them to survive repeated prophesies of their imminent demise. The next generation of systems design will see increased collaboration between traditionally discrete design teams, all working together to achieve the holy grail of optimized product performance in a small package at a reasonable cost. As a result, the lines between electronics disciplines may be blurred forever.
DAVID WIENS, director of business development, Systems Design Division, may be contacted at Mentor Graphics Corp. 1811 Pike Rd, Suite 2F, Longmont, CO, 80501; 720/494-1086; E-mail: firstname.lastname@example.org.