SiP and 3-D Interconnects


Integration schemes for Through-wafer Via Devices


The technical feasibility and unique potential of systems-in-a-package (SiP) and 3-D interconnects offer better performance due to reduced interconnect length and power consumption, smaller form factor, higher device density, integration of devices from heterogeneous substrates, and the capability to process different functional entities on different wafers, in different fabs and by different manufacturers; opening new possibilities for future devices. The focus now lies on innovative manufacturing and integration schemes, which meet both economic and technical demands. Vertical chip stacking can be performed as chip-to-chip (C2C), chip-to-wafer (C2W), or wafer-to-wafer (W2W) processes. Even though the fundamental principles of SiPs and 3-D interconnects are similar, the range of applications requires a variety of different manufacturing processes.

Aligned wafer bonding is the state-of-the-art technology for wafer-level layer transfer. Two fully processed wafers are aligned and bonded. The top wafer gets thinned down to a thickness of a few microns or below, and high aspect ratio vias are etched through the backside of the thinned wafer to provide vertical electrical connections between the two wafers. The electrical connections are only a few microns long, enhancing device performance. This process sequence, known as “via-last” approach, can be repeated several times. The alternative integration scheme, called “via-first,” allows double-side processing and via-formation prior to bonding, but requires a carrier wafer.

Modern production wafer-bonding systems integrate pre-processes into the wafer bonding platform to enable real-time process control (Figure 1). Accurate timing of the process flow optimizes the bonding process time, and results in increased capacity and throughput.

Figure 1. State-of-the-art wafer bonding platform with integrated cleaning, plasma activation, alignment, and wafer-bonding chambers.
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However, there are limitations. Both wafers must be the same size, but non-Si substrates are usually not available as 200- or 300-mm wafers. Additionally, MEMS fabs and foundries are mainly focused on 150-mm wafers, whereas logic and memory processing tends towards 300-mm. Only same-size die can be stacked without wasting substrate area. This may not be compatible with one key idea of 3-D integration - the capability to process different functional entities on different wafers.

C2W approaches don’t experience these limitations. As single dice are mounted on the base wafer, multiple die are mounted next to each other on one big base die. Via-first approaches are the preferred integration scheme for C2W. A metal-metal thermo-compression bond transforms the bond pads into electrical interconnects. For Cu-Cu bonding and the Cu-Sn solid-liquid-interdiffusion (SOLID) process, metal ion diffusion is the main bonding mechanism.

A new integration scheme, advanced chip-to-wafer (AC2W) bonding, targets these applications. As the diffusion rate is proportional to temperature, pressure, and time, it is impossible to perform the bonding as a single-die process. AC2W separates the bonding process into two sub-processes. The alignment and temporary pre-bonding are performed on a pick-and-place machine, whereas the permanent bonding of the dies is performed as a batch process in a dedicated bond chamber (Figure 2).

Figure 2. Advanced chip-to-wafer (AC2W) bonding: Schematic process flow.
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The AC2W bond chamber enables controlled process gas pressure or vacuum and programmable heating and cooling ramps. The permanent bonding process requires a controlled, homogeneous force to be applied on each chip. To accomplish this, the pressure plate is equipped with a flexible, compliant layer that compensates for any thickness variations between the top chips when applying the bond force via the piston and the pressure plate. Once the intermediate tacking material has evaporated or changed to liquid form as the system ramps up to final bonding temperature, reliable positioning of the chips is necessary before the permanent bond formation occurs. The selection of the compliant layer depends on the required final bonding temperature, the absolute thickness of the chip, and thickness variations between the top chips. The chip-to-wafer bonder focuses on the known good die (KGD) problem (Figure 3), which arises if non-working die on the bottom wafer are not bonded with any top device. The result is a possible shift in the center of gravity away from the center of the bottom substrate and requires a shift in the bonding process center of gravity. To address this, the center of force can be shifted within a 150-mm diameter. Different process technologies require different absolute force and variable coverage of the bottom wafer with top chips due to different-sized top chips, a bottom wafer with a different grid size, or variable yield. To handle these varied force requirements, the chip-to-wafer bonder enables programmable bond force from 150N up to 40kN. There are several fundamental differences between W2W and C2W approaches in terms of technology, economical considerations and manufacturability.

Figure 3. Shifted contact force due to known good die (KGD).
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In the 3-D community, yield is a controversial issue. C2W enables KGD to be used, whereas W2W requires every chip on the wafer to be used, including the bad ones. As one bad die can ruin the entire stack, yield control is important.

Single wafer yield: 3-D integration allows for the production of different functional entities on different wafers, reducing process complexity and number of steps. Particle exposure and yield loss due to particles correlates with the number of process and handling steps. Therefore process separation due to 3-D integration enables higher single wafer yield.

Particle-induced yield loss: 3-D die stacking enables a reduction in die size. Because particle density is independent of die size, reducing size reduces yield loss due to particles, and allows higher wafer area usage. Enhanced cleanliness for wafer-level processes compared to single-die processes is another side effect.

Die testing: To use KGD, it is necessary to test the dies. Testing dies directly prior to stacking would be optimal, but isn’t economically feasible. Wafer-level testing forces test prior to critical process steps like dicing, also reducing yield.

Die/wafer selection: In many applications an expensive wafer with multiple mask level, such as logic, is combined with a cheap wafer with fewer mask levels, such as memory. Due to the reduced number of mask levels and manufacturing steps, these wafers can be produced with a higher yield than the logic wafers. The key is to avoid stacking a bad memory die on a good logic die, whereas stacking a bad logic die with a good memory die is not that critical. It is possible to define tight yield specs for the memory wafer so as to not waste expensive logic dies.


Cycle time for wafer-level processes is independent of the number of dies on the wafer. So the more subsequent process steps, the bigger the throughput gain. The throughput for single-die processes scales with the number of dies. As the cycle time for wafer-level processes is nearly independent of wafer size, W2W shows even bigger throughput advantages for 300-mm wafers, whereas for 150-mm wafers, such as MEMS or compound semiconductor devices, C2W can be competitive for medium to large dies. For pick-and-place tools there is a trade-off between speed and accuracy. Figure 4 shows a throughput comparison for W2W and C2W. When chip count is only several hundred die, the high-speed C2W machines outperform the W2W approach for low-alignment accuracy requirements of 10 µm or above. However, high alignment accuracy on C2W comes always at the cost of throughput, due to the necessity for vibration damping and alignment control feedback loops.

Figure 4. Throughput comparison: W2W vs. C2W alignment.
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Post-bond Processing

Compared to other stacking and integration approaches, W2W allows further processing to be performed on fab equipment without any restriction, making it ideal for multi-stacks. Back-thinning after bonding is not different from wafer thinning. For some integration schemes, use of an SOI wafer enables buried oxide to be used as an etch stop, thereby allowing wafer thicknesses below 1 µm. For C2W integration schemes specialized equipment must be used. Back-thinning capability is limited, especially when the wafer is only partially covered. Mounting dummy dies on bad dies enhances the back-thinning feasibility, but comes at the cost of throughput.

Due to the high topography of C2W stacking, conventional spin coating results in poor uniformity of the resist layers and cannot be used. Spray coating is the state-of-the-art technique for such applications. The wafer-to-wafer thickness variation after back grinding is usually more than a magnitude larger than the depth of focus of modern steppers. Stacking chips from different individual wafers on one base wafer therefore imposes severe problems for using steppers. Proximity mask aligners are the method of choice as they don’t have a focal plane.

Thin-die Stacking

Some applications require double side processing prior to bonding. A novel thin wafer handling concept, based on temporary wafer bonding using a wafer handler, enables wafer thicknesses down to 1 µm. The subsequent processing is performed on standard equipment. However, the carrier wafer concept is only applicable for W2W integration schemes because of the time needed for attaching and detaching the carrier. Therefore the minimal layer thickness prior to bonding for C2W is limited by the mechanical stability of the substrate, which is in the order of several dozen microns.

High-density vs. Low-density Interconnects

Due to limited silicon real estate for interconnects, a higher interconnect density requires smaller bond pads together with high precision alignment processes. On C2W pick-and-place tools, high alignment accuracy comes at the cost of throughput. For economical reasons W2W approaches seem to be more suitable for high-density interconnects. Recently there have been studies on self-aligning mechanical alignment structures, which might be a promising approach for C2W and also W2W stacking.

Chip Design

Wafer-level stacking requires that chips of each stacking level be the same size. As a consequence, the chips must be designed specifically for each application or class of applications. The chip-to-wafer approaches allow chips of any size to be stacked. Therefore, it is possible to apply a real modular design and manufacturing process by using existing functional entities. C2W enables shorter time-to-market, reduced design costs and a higher flexibility for future device generations.

Although W2W and C2W integration schemes are competing approaches, the detailed analysis of the differences and similarities shows that for many applications, they are complementary methods. For complex devices a combination of W2W and C2W integration processes is a likely scenario.

Contact the authors for a complete list of references.

THORSTEN MATTHIAS and MARKUS WIMPLINGER may be contacted at EV Group Inc., 7700 South River Parkway, Tempe AZ 85284, USA; STEFAN PARGFRIEDER and PAUL LINDNER may be contacted at EV Group, DI Erich Thallner Strasse 1, A-4782 St. Florian, Austria. Email: