Flip Chip Technology


Mainstream At Last

BY JACQUES CODERRE, Universal Instruments

Over the years, flip chip has become the de-facto interconnection method for high-performance packages such as microprocessors, PC and graphics chipsets, high-speed memory, and high-end application-specific ICs (ASICs). In parallel, it has emerged as an effective interconnect solution for small I/O applications. Fueled by miniaturization and the acceptance of system-in-package (SiP), flip chip is considered the method-of-choice for various low-pin-count applications. Overall, adoption in both low- and high-end applications has translated into a forecasted 31% compound annual growth rate (CAGR) for solder-bumped flip chips (Figure 1).

Figure 1. Volume projections show strong growth in solder-bumped flip chips. CAGR of 31% projected.
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Flip chips appear in high-volume consumer products such as computer peripherals, mobile phones, digital cameras, and MP3 players. Semiconductor and circuit board assemblers boast about their ability to assemble these modules.

Two approaches now exist for module assembly in semiconductor back-end assembly factories. In the dual-reflow process, SMT components are first assembled on a separate SMT line consisting of a screen printer, a chipshooter machine, and a first reflow oven. The partially assembled modules are then processed through a second line consisting of a flip chip bonder and reflow oven. The underfill process is either performed in a dedicated underfill line, or coupled with the flip chip line.

Increasingly, assemblers are adopting a single reflow process, with flip chip placement operations integrated into the SMT line. The die-placement operation is performed by the flexible, fine-pitch machine, or IC placer, which handles chip scale packages (CSPs), wafer-level chip scale packages (WLCSPs), shields and connectors, and any other required components. Underfill is performed as a separate operation when necessary.

Figure 2. A SiP line consists of a solder-paste screen printer, a high-speed chip placer, an IC-placer with flip chip capability, and solder reflow oven.
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The simplified line consisting of a flip chip bonder and reflow oven has been replaced by a complex line of high-speed chipshooters and flexible machines that combine component and bare die capabilities (Figure 2). These new “convergence assemblies” drive the need for a placement machine that does not distinguish between SMT components and semiconductor devices.

Flip Chip Evolves on Two Fronts

The history of solder-based flip chip is linked to the evolution of the microprocessor and other high-performance ASICs. In 1969, IBM introduced its high-lead controlled collapse chip connection process (C4). Characteristics for a typical application included small ICs terminated by high-lead bumps; single-chip modules; no passive components; high-temperature co-fired ceramic (HTCC) substrates, which eventually migrated to a low-temperature co-fired ceramic (LTCC) version; and low coefficients of thermal expansion (CTEs). Solvent-based flux, needed for wettability, was dispensed on the substrate carriers and die were processed using vision-based bump registration. Solder reflow ensured reliable solder joint formation. Post-solder cleaning was the norm.

Reliability was predictable by means of the established Coffin-Manson equation, based on the CTE of the substrate and die. Over time, high-performance die grew in size, bump counts increased, and substrates got thinner. Underfill became a must. Later on, no-clean fluxes were introduced, and dipping die in a thin film of flux became a widely used fluxing technique. Accuracy requirements got tighter as bumps shrunk in diameter -12 µm or better became the norm.

In parallel, low-bump-count applications evolved, driven by miniaturization rather than performance. Low-performance requirements of such applications permitted the use of small bumps on tight pitches. As such, aggressive arrays in these small-bump-count packages have accuracy requirements of 10 µm or better.

Elimination of the package drives the effort to perform packaging operations at the wafer level. In a simple form, a redistribution layer is deposited which enables a fan-out of the bumps to a CSP pitch. Processes used for low I/O WLCSPs are reminiscent of early flip chip applications where underfilling was unnecessary. Without underfill, the component is processed as a standard array package at the board level.

Figure 3. Example of low-bump-count flip chip device on flex assembly. Other components include capacitors and a connector.
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As the pitch of CSPs, WLCSPs, and bare flip chip devices decrease over time, challenges are introduced. Die sizes below 3 mm and bump counts below 100 are frequent. Bumps counts below 10 are common. Accuracy requirements vary; components have either wide CSP pitches (300 µm or greater) where 25 µm is sufficient, or tight flip chip pitches (150 µm or lower) where an accuracy below 10 µm is needed. Other SMT components accompany logic devices. Passive components are small (0201s and 01005s). A passive/active ratio of 20/1 is typical. Other challenges include all-bump inspection, low-force placement, and high accuracy. High throughput is essential. Assembly tooling becomes critical to minimize die shifting during dip fluxing.

Dip Fluxing at the Board Level

Dip fluxing bumped devices, once solely used for flip chip assembly, has been adopted for other assemblies. At the board level, low-bump-count CSPs and WLCSPs are dip fluxed instead of being placed in solder paste. The trend is expected to continue as pitches decrease.1 Dip fluxing is also the method-of-choice in certain stacking operations. In package-on-package (PoP) for example, two or more CSP devices are mounted in a stack at either component assembly or board level (Figure 4). The industry seems to favor the latter due to supply chain logistics and cost control, and is ramping up in 3-G phone assemblies and other products requiring high-bandwidth digital signal processing.

Figure 4. Various PoP structures. Courtesy of ITRS 2005 Roadmap.
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CSP devices are dipped in either flux or paste prior to placement (Figure 5). The size of the components and solder bumps drive fluxing parameters that include: tight control of thick films of fluxes or paste; increased frequency of replenishment; integration into existing IC placers; high accuracy due to tolerance stack-up; and vision algorithms to permit layering of components.

Figure 5. High-speed fluxing of components using a linear thin-film applicator. Bumps are dipped in a high-tack flux.
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Stacks are expected to evolve in complexity. Bump pitches will tighten and the number of units in a stack will increase. Assembly equipment is expected to evolve along with technique.


Bumping. The lack of bumping infrastructure has been a hurdle facing the adoption of flip chip. This is no longer the case as bumping services are available in electronics assembly worldwide. Current issues pertain to the implementation of wafer bumping’s lead-free version. Bumping approaches such as C4NP offer a scalable solution to lead-free implementation.

High-density Substrates. The price of high-density substrates, once a deterrent to flip chip growth, has declined as volumes increased, enabling more applications to embrace the technology. A current infrastructure problem is one of capacity rather than price, and should resolve itself over time.

Assembly and Test. From an assembly and test perspective, worldwide circuit-board assembly infrastructure is leveraged, especially for SiP assembly. The use of flip chip for low-performance applications has reduced the relevance of yield-related issues, since wafer yields are high for simpler devices. Recent developments in wafer-level burn-in, and increased wafer yields, have alleviated test-related issues associated with flip chip, fueling the acceptance of the technology for multi-chip modules.


As flip chip becomes mainstream, novel ways to use the technology emerge. Although high-performance packages represent a portion of activity in revenue, it is the low-performance versions that fuel volume growth. Low I/O applications face assembly challenges that have evolved separately from high-performance counterparts. Newer applications drive a need for a “wall-to-wall” assembly solution, capable of placing a range of components found in both circuit board and semiconductor assembly.


Contact the author for a complete list of references.

JACQUES CODERRE, product manager for advanced semiconductor assembly, may be contacted at Universal Instruments, 33 Broome Corporate Park, Conklin, NY 13748; 607/779-4362; E-mail: