Wafer-level solutions for optical and sensor applications
By Juergen Leib, Ph.D., And Volker Seidemann, Ph.D.SCHOTT
Growing worldwide demand for smaller, lighter, and thinner consumer electronic products requires chip manufacturers to constantly find ways to miniaturize device packaging. One miniaturization method developed by chip manufacturers during the 1990s was chip size or chip scale packaging (CSP). More recently, manufacturers have expanded on the CSP process by packaging devices at the wafer level, fabricating and sometimes testing the full package on the wafer before dicing.
Most mainstream wafer-level packages (WLPs) fabricate the interconnect structure - usually solder balls - over the silicon device’s surface and mount WLP die face down on the printed wiring board (PWB). Such structures have served the industry well over the last decade, and these devices are found in practically every cell phone or portable electronic product on the market today.
Optical packages and most MEMS packages pose a problem for traditional wafer-level packaging techniques, because the device’s sensing function must be mounted face-up. This problem can be solved by having the active area of the sensor face-up with area array contacts for the interconnect on the backside of the device. With image sensor devices, the packaging must not only provide environmental protection to the top side of the device, but also be optically transparent.
Over the past several years, an optical WLP technology has been developed* that combines traditional WLP techniques with specialized glass and optic composition processes. This technology can be used for several types of optical sensor applications, including automotive, high-reliability, and MEMS cavity devices. Opto-WLP technology can also be used to produce image sensor (CCD and CMOS) devices, which are a key component in the fast-growing digital camera and camcorder market. A typical opto-WLP process sequence is shown in Figure 1.
Figure 1. Process sequence for opto-WLP.
Step 1: The devices are covered with a 500-µm glass cover sheet. Polished Borofloat 33 glass is often selected for the glass cover sheet, since it is a good CTE match to Si (3.25 ppm/°K), provides excellent optical performance, and has a high chemical stability. In addition, other glass cover plates, such as AF45s, can also be used.
The cover sheet is bonded to the device using an acrylic polymer adhesive or microstructured glass (MSG) technology to achieve a completely hermetic structure. In this case, a patented process** uses plasma-ion-assisted physical vapor deposition to deposit borosilicate glass through a photoresist mask (lift-off process) with substrate temperatures never exceeding 120°C.
Step 2: The wafer is thinned from the backside to about 100 µm, which enables low-profile optical packages.
Step 3: Via holes and dicing streets are plasma-etched simultaneously through a resist mask. Via holes have 70° sidewalls to enable subsequent lithography and sputter coating, and are cut down to the backside of the peripheral pads on the individual die.
Step 4: A plasma-enhanced chemical vapor deposition (PECVD) silicon oxide layer (or a microstructured glass layer) is deposited in the vias/streets at temperatures lower than 160°C. A second plasma-etch step through photoresist selectively removes the deposited oxide and the ILD oxides from the bottom of the vias/streets until the backside of the pad metallurgy is exposed. Insulator and metal redistribution traces are then deposited and contacted to the backside of the pads through via openings.
Standard benzocyclobutene (BCB)/Cu is typically used for this redistribution, although other polymeric insulators can and have been used. Aluminum can also be used as a redistribution trace.
For a completely hermetic package, one or both of the layers of BCB dielectric can be replaced by deposited glass. This process is generally used for packages that must pass MIL-std 883 hermeticity tests. An optical micrograph of the interconnect traces formed on the back of the thinned die is shown in Figure 2.
Figure 2. Interconnect and solder bumps on the backside of die using Cu/BCB redistribution.
Step 5: In the standard process, lead-free preformed solder balls are deposited on the Ni under-bump metallization (UBM) of the solder pads. These contacts on the backside of the wafer can be adapted to the specific needs of the board assembly process using preformed balls.
Figure 3. Opto-WLP in cross-section.
Step 6: The die are singulated through the previously exposed dicing street. Figure 3 shows a cross-section of the completed opto-WLP package. Figure 4 shows an imaging sensor packaged using opto-WLP technology.
Figure 4. Imaging sensor packaged using opto-WLP technology.
Opto-WLP for Camera Modules
Particles are the primary cause of yield loss in camera module assemblies. It has been reported that 90% of defects are related to particles and 80% of these are due to particles on die. Wafer-scale packaging using hermetic opto-WLP technology decreases these defects significantly, and allows for further assembly in a low-grade cleanroom atmosphere. Design rules can be relaxed, unlike other optical CSP designs where leads must wrap over the die edge to the back surface, constraining lead count and pitch.
In the future, it will be possible to produce thinner camera modules by using opto-WLP technology to integrate the IR filter and possibly even the lenses into the package stack.
Opto-WLP technology is a new way to package devices used in optical and sensor applications. The process first bonds an optical cover glass to the active side of a device wafer, forming a glass silicon sandwich. Then, after thinning the wafer and etching tapered sidewall vias through the backside of the silicon, existing peripheral pads can be connected to the backside of the device using standard redistribution technologies. Alternatively, a completely hermetic package can be fabricated using microstructured glass as the insulator. By combining this technology with high-yielding thin-film processes, chip manufacturers are able to commercially produce high quantities of optical and sensor devices.
*by SCHOTT and Fraunhofer-IZM Berlin
Contact the author for a complete list of references.
JUERGEN LEIB, Ph.D., director of technology, may be contacted at SCHOTT Advanced Packaging Singapore, 2 Woodlands Sector 1 #01-20, Woodlands Spektrum 1, Singapore 738068; 65/6853-8030; E-mail: email@example.com. VOLKER SEIDEMANN, Ph.D., manager of research, may be contacted at SCHOTT Electronics, Gustav-Meyer-Allee 25, Building 17a, D-13355 Berlin, Germany; 49/3046403-618; E-mail: firstname.lastname@example.org