IC and Package Co-design
Dos and Don’ts of Wire-Bond Assembly
By DarrenMaxwell-Davis, Singulated Technology, John Sovinsky, CAD Design Software, and Curtis Escobar, Corwil Technology
Multiple rows of die pads and stacked die in high-density chip scale packages (CSPs) demand a robust system of die, wire, and substrate co-design. Although advanced 3-D modeling and checking routines in modern electronic design automation (EDA) software helps overcome some of the limitations of a poor IC design, there are general dos and don’ts of die and substrate layout for wire-bonded components.
Do put all power and return (VDD and VSS) die pads in the outer row of the die.
Outer power and return pads create the lowest inductance path that is easiest to wire-bond, has the least wire-to-wire interference, and can use a larger diameter down-bond wire. Typically, the grounds are in the innermost bonding ring on the substrate.
Do put pairs adjacent to each other in the same row of die pads.
To create a similar electrical model for pairs, make sure bond wires have the same shape and size. This is best achieved by placing pairs in the same row of die pads adjacent to each other. If possible, keep a little extra space around the pairs, or put very low priority signals next to the pairs on the die.
Do group critical signals and classes with regard to the underlying PCB layout.
Address these questions before finalizing the die layout: Will any signals need termination on the BGA substrate or underlying PCB? Do any signals need to be placed near the edge of the BGA substrate? Are there any plane splits beyond standard VSS and VDD? Do any signals require very short traces/very low inductance or resistance?
To place components close to signals on the PCB, connect them to the outer edge pins of the BGA substrate.
Don’t push industry assembly paradigms in the prototype.
Excessively reducing die-pad pitch may result in die-bonding pads that are too close for effective assembly. Pushing the minimum wire-bonding pitch can reduce yield, signal integrity, and device performance without resulting in a corresponding reduction of the package size.
Large-diameter bond wires increase performance by reducing inductance and resistance. Large die pads on large pitches help assembly and allow largest possible wires use. Bond wire may be longer when the diameter is larger. When wire-bond pads on the die are spread out and enlarged, wire-bond pads on the BGA or COB substrate may also be spread out and enlarged. In addition, enlarged substrate bond pads may be required for double bonding (two wires on a pad). When substrate bond pads are spread, more diverse patterns and rows of bond pads may be used for a variety of unique design features or requirements.
Figure 1. Spreading substrate bond pad rows provides room for blind vias between the rows.
Blind vias may be added between substrate bond pads to use denser BGA matrices (Figure 1). Special voltages may be made more robust or used to build shield structures, guard rings, and planes (Figure 2). Smaller BGAs have better signal integrity. When blind vias are used, wire-bond pads may be positioned over BGA balls without sacrificing flexibility in assigning balls to pins.
Figure 2. VDD pullbacks surround differential pairs.
Adding a few microns to the nominal die pad pitch may result in a better, smaller, high-performance custom BGA because bond wires can be better spread and use longer wires. If the die is going to be reduced in size after prototyping, spreading die pads equally to the widest reasonable pitch will make prototype assembly easier.
Don’t procure substrate without strict attention to assembly rules.
Maximum wire lengths can vary from 3 to 11 mm, and in most cases have conditions relating to bond pad density, die height, and number of bonding rings and rows. Procuring a substrate without regard to assembly rules and practices can lead to unfortunate surprises when the substrate is delivered to the back-end IC assembly vendor. If a wire-bond design manual is unavailable, address these questions before finalizing die and substrate layouts. Is there a nominal and minimum die bond pad size/pitch? What is the preferred and minimum substrate bond pad width? Is the longest wire nominal and small-quantity? Can the majority of wires be considered longest? What is the wire loop height at longest and shortest wire? How many different wire diameters and shapes can be used on one die (Figure 3)? A sub-optimal die layout combined with a substrate layout that makes wires too long or in violation of other size and pitch rules can be the difference between low yield and “no bid”.
Figure 3. Jumbled bond wires are the result of a poorly designed die.
Do spread wires for yield.
Die with two or three rows of wire-bond pads are subject to greater failure during bonding and encapsulation. Since bond wires can be as little as one to two times the wire diameter distance from each other over the die, the ideal design will have the largest distance and most consistent wire shapes.
The perfect multi-row bond-out will have all bond wires uncrossed, regardless of profile. In practice, most wire tiers (inner vs. outer rows of die pads) will have to cross when viewed from above in order to conform to substrate physical rules and electrical requirements.
The entire die, wire, and substrate system should be modeled in 3-D for advanced design rule checking, including the bonding capillary, to optimize the package yield rate (Figure 4). Maximum wire length, profile (3-D trajectory), and form factor (height) will impact the degree to which wire bonds can be spread.
Figure 4. An assembly-friendly die stack combined with rules-driven substrate design, fabrication, and wire bonding.
Do design substrate for implementation.
Substrate cost and lead time are largely determined by the most difficult-to-manufacture vias, combined with trace size/space and signal integrity requirements. Addressing substrate fabrication before finalizing die design can help set the prototype calendar. When deciding between traditional plated through-hole or blind/buried vias, keep in mind the possible implications to fabrication, assembly, and performance.
Since wire-bonding specification will drive the substrate wire-bond pad sizes and pitch, vias should also be designed as part of the die-wire-substrate system.
Additional Areas to Consider
Design for lifecycle: Prototype implementations may tolerate a larger package to reduce cost and time to procure.
Design for signal integrity: High frequencies and speeds may drive layout of package and end PCB.
Design for compatibility: Will the package solution conform to JEDEC, or another type of standard pin-out?
Design for test: Will automatic testing drive packaging solutions, trying for the smallest number of device under test (DUT) PCBs?
Netlist vs. Physical-electrical Design
Some device types trend toward standardized package pin-outs, while others focus on optimizing signal integrity in a prescribed form factor. Component and prototype qualifications must be considered, as well as the acceptable amount of gate or pin swapping. Whether prototype or production design is driven by a standard net list, gate and pin swapping, the PCB design, automatic test requirements, or other factors such as end-customer preconceptions must be carefully weighed.
As custom BGA design emerges as a dominant methodology for packaging ICs, front- and back-end vendors must cooperate to enhance the value of each component or multiple-chip system. Prototype substrate and assembly solutions may differ from the final production version. A large part of optimizing return on investment (ROI) is determining and implementing cost-effective solutions for prototype and production quantities of wire-bonded devices (Figure 5). The more wire-bond-friendly a die bond-out is, the better the value, performance, and turn time.
DARREN MAXWELL-DAVIS, president, may be contacted at Singulated Technology, 2745 Orchard St., Soquel, CA 95073; 831/295-3530; E-mail: firstname.lastname@example.org. JOHN SOVINSKY, CTO and founder, may be contacted at CAD Design Software, 1731 Technology Dr., Suite 340, San Jose, CA 95110; 408/436-1340; E-mail: email@example.com. CURTIS ESCOBAR, senior assembly engineer, may be contacted at Corwil Technology, 1635 McCarthy Blvd., Milpitas, CA 95035; 408/321-6404; E-mail: firstname.lastname@example.org.