From Current to Next-generation Materials
By George Carson, Ph.D., and Michael Todd, Ph.D., Henkel
Since its origins at IBM in the 1970s, underfill technology has been part of the electronics manufacturing landscape. Originally used with ceramic substrates, underfill systems were not widely adopted until the industry shifted from ceramic to organic (laminate) substrates, heralding the need for organic underfills - the industry standard.
There are three types of underfill systems currently in use: capillary underfills, fluxing (no-flow) underfills, and 4-corner or corner-dot underfill systems. While all have their advantages and limitations, capillary underfills are the most widely used of these materials.
Used for a variety of applications including flip chip on board (FCOB) and flip chip in package (FCiP), capillary underfills provide reliability enhancement by equally distributing stress across the chip’s surface. Capillary underfilling of traditional flip chips and chip scale packages (CSPs) are very similar processes. The chip is attached to the substrate onto deposited solder paste attachment sites, is reflowed, and a metallic interconnection is formed. Following this process, underfill material is applied using dispensing technologies to one or two of the edges of the CSP (Figure 1). Material flows underneath the package and gaps between the CSP and substrate are encapsulated.
Figure 1. Capillary underfill is applied to device edges.
While the use of capillary underfills have significant reliability-enhancing advantages, incorporating them into the manufacturing process requires dispensing equipment, floor space to house the equipment, and dedicated operator staff. Because of these investment requirements and the need for time-saving enhancements, fluxing (no-flow) underfill technology was introduced.
The primary advantage of no-flow underfill technology over other underfill systems is process improvement, as opposed to significant material property enhancements. Designed to make underfilling more conducive to traditional surface mount assembly processes, no-flow underfills essentially eliminate the need for a dedicated curing oven. By incorporating the fluxing function in the underfill, CSP attachment and material cure are combined into one step. During the assembly process, no-flow underfill is applied to the CSP attachment site before the component is placed. When the board goes through reflow, the underfill performs as the flux, allows the metallic interconnection to form, and completes cure in the reflow oven. So, underfilling can be achieved in the course of traditional assembly process steps (Figure 2).
Figure 2. No-flow underfill process delivers advantages.
While no-flow underfills provide substantial cost and time savings from an equipment and personnel investment standpoint, there are some limitations. Unlike capillary underfills, no-flow materials are unfilled products by necessity. Filler materials in underfills can hinder contact between the solder balls and pads. By design, therefore, these systems are absent of particles to promote better solder joint formation during reflow. Without these particles, the coefficient of thermal expansion (CTE) is high, so thermal cycling performance is not as robust as that of capillary underfills. Also, being processed through traditional reflow can result in yield disadvantages if the process is not carefully controlled. Moisture trapped in the boards can escape during reflow, causing voids. However, new technology shows great promise for resolving these issues.
Figure 3. Corner-dot underfill is an alternative for certain applications.
For applications such as CSPs with interposers, or corner arrays that are not as conducive to capillary flow or no-flow underfill systems, corner-dot underfill provides an alternative. This technology involves dispensing pre-applied underfill at the corners of the CSP pad site (Figure 3). Like no-flow underfills, corner-dot technology can be incorporated using existing assembly equipment resources and cured during normal solder reflow. Because these underfills are reworkable, manufacturers also can avoid scrapping an entire assembly if there is only one defective device.
Technology Shifts Demand Reliability Enhancements
The importance of underfill technology in next-generation electronics applications has become even more pronounced as devices and pitches become smaller and more demanding and lead-free process requirements come online.
Underfills provide high levels of reliability for lead-free solder joints for CSPs, which are more vulnerable to failures caused by CTE mismatches than their tin-lead predecessors. Because substrates have more likelihood of warpage due to lead-free’s higher processing temperatures, and lead-free solder alloys having lower ductility, failure rates for lead-free solder joints are higher. The move to lead-free manufacturing and resulting solder-joint brittleness has made underfilling these devices the most cost-effective and viable solution for enhancing reliability.
As we move toward pitches of 0.3 mm for CSPs and <180 µm for flip chip packages and smaller, underfill materials may be the only way to ensure maximum end-of-the-line yield.
The Shape of Things to Come
In addition to ensuring high reliability in the face of changing mechnical requirements, electronics firms must do so at a competitive cost. To address these challenges, new underfill technologies have been developed and, though still in their infancy, are showing great promise.
No-flow underfills deliver advantages in terms of process efficiency and reduced equipment and personnel costs. But these benefits can be outweighed by technical issues encountered from using an unfilled material. However, a no-flow underfill system with 50% filler content has recently been introduced to the market. This filler percentage delivers the thermal cycling advantages of filled materials, while also maintaining the streamlined processing gains of no-flow technology.
Another innovation that has garnered a lot of attention is pre-applied underfill technology, which has the potential to eliminate the entire underfill process for the back-end. Applied to the CSP before board-level assembly, or to the die interconnect at the wafer level, the concept of pre-applied underfill is sound, but when put in practice with today’s production requirements, presents some processing challenges.
Figure 4. Pre-applied underfill application processes.
At the wafer level, the pre-applied underfill could be applied either prior to bumping or after bumping, both of which require very tight process control (Figure 4). If the material is applied before bumping, it must be process-compatible. Conversely, application after wafer bumping demands that the pre-applied underfill material does not coat or damage the bumps. Other considerations, such as underfill integrity during the wafer-dicing process and product stability over time, must also be evaluated. While a few suppliers’ research and development for pre-applied underfill technology is quite advanced, further research is required to bring this technology into mainstream viability.
Without underfill materials, it is certain that today’s fine-pitch devices would suffer reliability issues. Furthermore, the process and temperature demands of lead-free manufacturing call for underfill materials to improve failure rates arising from CTE mismatches in lead-free solder joint connections.
New process requirements, coupled with increases in device functionality and reductions in package form factors, necessitate increased use of robust underfill systems. And, while there are several types of viable underfill technologies, further development of next-generation, cost-efficient, process-enhancing materials technology is required if electronics products are going to continue delivering the benefits of high function and low cost.
Contact the authors for a complete list of references.
GEORGE CARSON, Ph.D., technical director of application engineering; and MICHAEL TODD, Ph.D., director of research, development, and engineering for material sets, may be contacted at the Electronics Group of Henkel, 15350 Barranca Parkway, Irvine, CA 92618; 949/789-2500; E-mail: firstname.lastname@example.org and email@example.com.