In the News
F&K Delvotec Partners with Siemens for Die Bonder Series
OTTOBRUN, GERMANY - F&K Delvotec recently announced that its die bonder product series has been acquired by Siemens’ Automation and Drives. All die bonder activities, including R&D, manufacturing, service, and consulting, will be incorporated into the Siemens’ Electronics Assembly Systems Unit, Optical Solutions, in Nuremberg, Germany. Combining F&K Delvotec’s know-how in wire and die bonding with Siemens’ experience with chip assembly and high-speed manufacturing will help to meet customer requirements in electronic module production, medical industry, and flight technology.
“The electronics manufacturing market is moving toward integrated solutions in which component placers and die bonders become a single unit,” states Farhad Farrasatt, Ph.D., president of F&K Delvotec Bondtechnik GmbH. “Siemens and F&K Delvotec can now supply these increasingly requested solutions from a single source.”
At the Ottobrunn headquarters, F&K Delvotec will focus on the wire-bond business, and recently introduced an AOI post bond inspection solution, says Manfred Philipigh, sales and marketing manager Europe, F&K Delvotec.
SMTA Wafer-level Packaging Conference Set for November
MINNEAPOLIS, MN - The Surface Mount Technology Association (SMTA)’s third annual International Wafer-Level Packaging Conference (IWLPC) is set for November 1-3, 2006, at the Wyndham Hotel in San Jose, CA. Wilfred J. Corrigan, founder of LSI Logic and internationally known semiconductor industry statesman, will present the keynote address at the dinner presentation scheduled for Thursday, November 2nd at the Wyndham.
The show will consist of one day of workshops and two days of presentations and panels on 3-D packaging, system-on-package (SoP), MEMS, and chip scale packages, and includes a tabletop exhibit show featuring approximately 50 exhibitors from companies in the packaging industry. Back by popular demand will be a panel on market trends in packaging, with presentations by the semiconductor industry’s leading market forecasters. Last year, most show attendees attended the panel presentation. Speakers for this year’s panel are yet to be chosen.
Since its inception 21 years ago, SMTA has been dedicated to providing assemblers revolutionary solutions that began with SMT, says Ken Gilleo, SMTA VP of technical programs. When future breakthroughs such as BGA and CSPs came along, SMTA provided sessions, workshops, and symposia to help members adopt new technologies. “SMTA, in partnership, continues to deliver programs to help members understand and utilize important new technologies,” notes Gilleo. “The IWLPC is one example of our dedication to delivering leading-edge knowledge.”
Zuken, Altera Sign Design Program Agreement
MUNICH, GERMANY, and WESTFORD, MA - Zuken, an engineering consulting company, has signed a design program agreement with Altera Corp., a system-on-a-programmable chip (SOPC) solution provider. The Altera Commitment to Cooperative Engineering Solutions (ACCESS) program ensures a solid design methodology to develop FPGA and structured ASIC designs by enabling close interoperability between third-party tools and Altera’s Quartus II development software. Participation in this program supports Zuken’s ongoing commitment to provide a comprehensive set of design tools tailored for applying next-generation programmable logic devices (PLDs) on PCBs.
“We are committed to increasing the capability of our tools within the FPGA and structured ASIC environment,” comments Gerhard Lipski, general manager of Zuken Europe and CEO of Zuken USA Inc. “This strategic partnership will pave the way for collaborative projects that will eliminate unnecessary design work required by the growing number of companies using sophisticated PLDs on PCBs.”
“We welcome Zuken to the Altera ACCESS Program,” adds Jim Smith, Altera’s director of electronic design automation (EDA) relations. “Zuken’s constraints-driven tool suite addresses the high-speed board design and manufacturing needs of our programmable and structured ASIC customers.”
WELLS-CTI, DCI, and DB Design Form UMD Advanced Test Technologies
VANCOUVER, WA - With the acquisition of Dimensions Consulting Inc. (DCI) now complete, UMD Technology Inc., a provider of semiconductor test solutions, has announced that it is poised to enter the market as UMD Advanced Test Technologies, forming the first back-end IC test consumables company to offer burn-in sockets, ATE consumables, and thermal management solutions in one place. Previous acquisitions of WELLS-CTI, a supplier of burn-in sockets, and DB Design, a provider of provider of test interface solutions, set the stage for the three-company integration.
“The introduction of UMD Advanced Test Technologies is a serious response to the market’s fervor to reduce the overall cost of semiconductor test. We believe in order to significantly reduce the cost of test, we as an industry must get smarter and offer innovative solutions that not only reduce the cost of capital, but dramatically improve yields. This will require a coordinated effort and expertise in a range of engineering and market segment disciplines,” states Matt Bergeron, UMD’s CEO. “Integration of like disciplines is no longer optional; we must pull from multiple areas of expertise to achieve the results the market requires.”
The three-company acquisition and merger is a strategic undertaking that began in March 2003 with the acquisition of WELLS-CTI, and closed in February 2006 with the purchase of DCI. The newly formed UMD Advanced Test Technologies will target yield and the integration of like disciplines to reduce the cost of test and get new devices moved to market faster.
“With the integration of WELLS, DB, and DCI, we will develop key centers of expertise that will allow us to attack high-sensitivity areas and introduce new solutions and technologies that the test and burn-in markets are demanding,” states Mark Murdza, UMD’s director of marketing.
Tessera Names Executive VP for Product Division
SAN JOSE, CA - Tessera Technologies recently named Mike Bereziuk as executive VP of its product division, which includes the San Jose-based product miniaturization division and the newly acquired wafer-level packaging center formerly owned by Shellcase Ltd., located in Israel.
As head of Tessera’s technology and services businesses, Bereziuk brings 26 years of semiconductor industry experience to his position, and will be responsible for driving Tessera’s growth through its technologies, such as its chip scale, multi-chip, and wafer-level packaging products. Reporting directly to Tessera’s chairman, president, and CEO Bruce McWilliams, he succeeds Nicholas Colella, who will also report to McWilliams in his new role as senior VP of corporate strategy.
Bereziuk spent 16 years at National Semiconductor Corp. in various senior operations, sales, and marketing roles. Most recently, he was senior VP and general manager of the worldwide sales and marketing organization, and was responsible for demand creation and order management for the company’s global customer base.
Packaging Research Center SoP Open House Highlights Vision
By Françoise von Trapp
Sharing his vision for system-on-package (SoP), a 3-D integration concept for lower-cost, smaller, and better performing multi-functional devices, Rao Tummala, Ph.D., director of Georgia Institute of Technology’s Packaging Research Center (PRC), welcomed 50 attendees to an open house and seminar, titled “Next Generation of Microelectronics Systems and Packaging Technologies: System-on-Package,” on March 13, 2006. The PRC hosts the biannual event to introduce first-time visitors to its vision and strategy in microelectronics and packaging research.
During his presentation, Tummala explained the PRC’s comprehensive and industry-centric approach. As a national center for convergent systems from 1995 - 2006, PRC researches, explores, develops, and demonstrates the SoP’s concept, educates a new breed of engineers in SoP, and develops strategic partnerships within the industry. “We produce the best engineers in the area because of their view of the world tomorrow,” stated Tummala.
The PRC’s vision takes packaging beyond Moore’s Law, applying a System Integration Law (Figure 1), where system-on-chip (SoC) achieves the highest level of on-chip integration, system-in-package (SiP) reaches the highest level of IC package without packaging integration, and SoP goes beyond SiP with IC package integration, explained Tummala. This drives the development of multifunctional, highly miniaturized, and lower-cost multifunctional devices. “SoC is a chip, SiP is a module, and SoP is a system,” summarized Tummala.
Figure 1. PRC’s law for systems integration.
PRC’s vision of second-generation SoP requires the integration of electrical, chemical, biological, mechanical, and thermal disciplines to realize megafunctional systems. Five research alliances: embedded RF, embedded optoelectronics, embedded digital, wafer-level packaging (WLP) and assembly, and 3-D SoP, help realize this vision.
Farrokh Ayazi, associate professor, College of Engineering Integrated MEMS Laboratory, shared inroads on MEMS and sensor research involving integrated “smart” microsystems. His team is developing a WLP wireless biosensing platform for the electrical detection of environmental substances. Future applications include: clinical diagnostic sensors for the early detection of cancer; and environmental sensors used to detect salmonella, botulism, Ricin, anthrax, and chemical toxins within the food and security industries.
John Papapolymerou, associate professor, Electromagnetics and Electronic Design and Applications, presented research on embedded RF SoPs. His team focuses on the development of ultra-compact module technology for RF wireless systems. This project requires interdisciplinary research such as vertical transition, embedded ICs, liquid-crystal polymer (LCP), and RF MEMS. NASA is interested in this technology for MEMS switches to provide different frequencies for rain/snow sensing from space.
Most recently, PRC focused on launching thematic consortia program memberships to target multiple research areas. Topics include Mixed Signal Design Tools, Embedded Actives and Passives, Thermal Interface Materials, Electrical Test for SiP/SoP, and Nano Materials and Packaging. Research stems directly from industry needs. Rather than concentrating on new developments in their discipline, students approach solutions collaboratively. For example, a materials science student researching material sets will be partnered with both electrical and mechanical engineering students to ensure the resulting technology can be implemented in real-world applications.
Dean Sutter, associate director of infrastructure at PRC, offered attendees a facility tour. The PRC lab is a full-fabrication facility. As an infrastructure partner, companies donate equipment, materials, or processes, and benefit by having their particular products or services used in leading-edge research, explained Sutter. Each relationship is individually managed within established guidelines with possibilities for interaction with the PRC, ranging from full donation to full purchase with significant educational discount, or a combination of the two, as long as the product or service offered is needed to meet the strategic goals and objectives of the PRC, as well as yielding benefit to the company.
Flip Chip Presentation Draws Local IMAPS and SMTA Members
BOXBOROUGH, MA - For the second time this year, SMTA Boston and IMAPS New England members shared ideas and information over dinner in a joint meeting and presentation, held March 21, 2006, at the Holiday Inn Boxborough Woods. The evening’s program included a presentation titled “Flip Chip Technology - What, Why, and How?” by Daniel Baldwin, Ph.D., Professor of Mechanical Engineering at the Georgia Institute of Technology, and co-founder of Engent, provider of advanced electronic manufacturing and thechnology services. Baldwin also serves on Advanced Packaging’s Editorial Advisory Board.
Baldwin discussed the flip chip process and different bumping methods, including C4; copper pillar bumping; gold wire stud bumping; conductive adhesives; and electrochemical, electroless, and gold plating. He cited one challenge as the thermal expansion difference between the chip and the substrate, although flip chips have a more efficient thermal path than wire bonding.
With all the variation in flip chip processes, only a few have proven reliability. For commercial applications, reliability data looks good. Where lead-free issues are concerned, some say it’s better while some say worse, says Baldwin. It could go either way. “Flip chip devices have been more scrutinized than any other packaging configuration of all time,” noted Baldwin, “and we still don’t know how they’re going to behave.”
Devices that have converted to flip chip include microprocessors, disk drives, and high-performance RF devices. One example Baldwin discussed that incorporates flip chip and wire bonding technologies is an implantable RF sensor used to track the migration patterns of fish. Other niche applications include an implantable retina model that uses a flex prosthesis mounted within the eye, a flip chip hearing aid with flex circuits mounted in the ear canal, and RFID tags that use flip chips attached with conductive adhesive to an etched copper antenna.
Cost, higher I/O counts, performance requirements, miniaturization, system integration, and thin form factor are all driving factors in flip chip conversion. Flip chip offers a depreciating infrastructure for wire bonding because it takes only a small modification to wire bonders to convert them to stud bumping, a reliable flip chip method.
In conclusion, Baldwin outlined pros and cons of flip chip methods. They provide 2-D density, and are fully SMT-compatible and repairable high-performing electrical interconnections. On the down side, they are not easily inspected, require underfill, and there are issues with known good die (KGD).
In February, SMTA Boston and IMAPS New England held a joint event that featured a presentation by Jennifer Bailey of Sonoscan, entitled “Practical Applications of Acoustic Micro Imaging” (AMI). They will team up again during the IMAPS New England 33rd Annual Exhibition and Symposium, May 16, 2006, where SMTA will hold an SMT technology session.