Issue



Semiconductor Roadmap: The Bottom Line


04/01/2006







The International Technology Roadmap for Semiconductors (ITRS) is the primary means for the semiconductor industry to move forward in some kind of orderly manner, with everyone looking at the same guideposts as they push technology ahead. The latest version of the ITRS was released at the end of 2005, with its annual update from the international team of experts gathered by the Semiconductor Industry Association (SIA). I look forward to seeing the consensus on the biggest issues facing the industry. This installment of the ITRS put the cost issue at the top of the list for packaging.

The ITRS begins with its list of industry-wide “grand challenges,” which is a selection of major “difficult challenges” reported by each of the 15 working groups that cover different segments of the industry. In the previous major update - there is a “major” update every 2 years and a less extensive update in the intervening years - the two packaging topics cited as “grand challenges” were chip/package co-design and packaging of Cu/low-κ chips. Those two fell off the list in 2005, and the only packaging topic left was “Meet the Changing Cost and Performance Requirements of the Market.”

In the past, I noted that “cost-per-pin” is a prominent piece of data included in the tables that project the requirements for packaging, while there is no such cost metric in other industry sectors. Why pick on packaging so much for costing something? This reflects the historical viewpoint that because packaging adds virtually no value, any cost incurred goes directly to the bottom line as a negative. This view has changed recently. Most people understand, for example, that cell phones as we know them would not be possible without recent major advances in packaging technology. So, packaging must be worth something if it enables a product that ships 800 million units per year.

In spite of all of the progress by the packaging industry that allows something like a cell phone to be a virtually disposable item, the assembly and packaging section of the ITRS notes tremendous opportunities for progress, saying “Today, assembly and packaging is a limiting factor in both the cost and performance for electronic systems.” In response to this, according to the ITRS, innovation is accelerating, but the investment needed to meet requirements on the roadmap is “greater than current run rates and cannot be met through the current gross margin of the packaging and assembly suppliers.” This gap is singled out as the greatest challenge for the packaging sector. Basically, much more money needs to be invested to drive down the cost of packaging further.

On the positive side of packaging cost, the only “grand challenge” remaining is that technical challenges are apparently being addressed. Citing “signs that the technical community is responding,” the ITRS highlights encouraging progress on many fronts, including an increase in university research on packaging; venture capital funding in the packaging arena; government and private research programs; and investment by IC makers in new packaging technology for their products.

However, there are plenty of technical challenges left for the industry. Since the last major revision in 2003, the updated list of “difficult challenges” for assembly and packaging shows near-term challenges growing from five to 10 topics, with two of them moving from the long-term list to the near-term list in the last 2 years. The two areas of accelerated challenges are 3-D packaging, and the gap between chip and substrate technologies. Other new items on the near-term challenge list include wafer-level, thinned-die, and flexible-system packaging. The long-term challenge list includes packaging of emerging device types, with organic devices, biochips, and nanostructures given as examples of chip technologies that will require novel solutions.

The first item on the long-term difficult challenges list is still the bottom line - package cost does not follow the die cost-reduction curve. The emergence of wafer-level packaging addresses this somewhat by leveraging the cost benefits of batch processing, but the applications where this is applicable and cost-effective are still limited to high-yielding, low-pin-count, small-size die. The industry still needs other high-volume manufacturing solutions, as well as new business models, to ensure that the packaging cost does not become a permanent roadblock on the ITRS roadmap.

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JEFFREY C. DEMMIN, Advanced Packaging contributing editor, may be contacted at Tessera Technologies Inc., 3099 Orchard Dr., San Jose, CA 95134; 408/383-3691; E-mail: jdemmin@tessera.com.