Issue



Socket Technology Validates High-frequency Devices


04/01/2006







A method was developed that allows a socket to be soldered in place of the package within the same footprint. Once mounted, the socket is ready to accept any device with the matching ball pattern. This method reduces the time and effort required for high-frequency device validation; a major concern of package developers.

BY JAMES RATHBURN, GRYPHICS INC.

As the industry transitions to next-generation memory devices and new memory modules, silicon and package developers face unique challenges that didn’t exist with previous generations of DRAM. Device speed advancements and increased system-level bus architecture performance create a situation where signal performance is a major concern. As new, faster devices are mounted to a memory module (in the case of DRAM) and plugged into a motherboard socket, understanding component signal performance in the path becomes critical. When the platform or silicon is analyzed, it may be difficult to determine the source or location of a signal integrity issue. The problem could be in the silicon, package, or SMT soldering process where the device was mounted, or in the routing or grounding scheme of the PCB itself. Reworking or replacing a device on the module without introducing additional problems is a daunting task, and traditional means of socketing devices can no longer pass high-frequency signals. However, one method reduces the time and effort required for high-frequency device validation.

The Past, Present, and Future of Memory

The memory IC industry has gone through major changes in recent years. Many suppliers constantly battle with pricing and performance. Past system bus architecture allowed most DRAM products to function at lower speeds without significant issues, but as the transition is made to high-frequency, low-voltage, differential-signal architectures, the issues associated with implementing high-speed memory are of concern. The industry is transitioning to DDR2 and fully buffered DIMM memory devices and modules, with new generations on the horizon. Table 1 lists performance specifications and signal integrity requirements for current and future devices. As new, high-frequency devices and system architectures are developed and deployed, it is critical that the signal path from the chip to the system is designed, validated, and optimized to reduce failure risk.


Table 1. Memory device specifications.
Click here to enlarge image

null

Historical Test Methods

Device manufacturers and system designers have had a variety of tools available to validate performance. When new silicon is available, the device is either soldered to the module or system board, or assembled with the use of a connector or socket. Often, the system or silicon validation groups must send the PCBs and devices to another department or facility for rework, resulting in low yields. The assembly can be damaged, or a nearby device upset during reflow, especially with the higher temperatures required for lead-free solder processing. Socketing the device makes it easier to mix and match, or remove and replace devices, as the silicon is tested and verified. There are two main types of sockets that can fill this need: one that is soldered in place of the device, or one that is mounted without solder with the use of fasteners. The socket, which is screw-mounted to the PCB, can pass signals electrically, but is generally too large for most memory applications, and requires a board redesign to allow for alignment and fastener holes. When a socket is used, it typically has been a style where a receptacle is soldered in place of the memory device, and the device itself is soldered to an adapter, which plugs into the receptacle. This type of socket adds significant height to the assembly, and will not cleanly pass the signals required for next-generation devices.


Figure 1. DDR2 memory device socket.
Click here to enlarge image

null

New Methods Required for High Frequency

A socketing method was developed that allows the socket to be soldered in place of the device within the same footprint - or shadow - as the device so that nearby discrete components, routing, and overall PCB layout were not impacted. The socket technology must not add significant height to the assembly, since many of the applications would be plugged vertically into a system and must not hit each other. The socket must be able to pass required signals with low insertion loss (less than -1 dB) beyond 10 Gbps. The resulting technology, shown in Figure 1, was developed in conjunction with end users so they could solder a socket that was the same size as the BGA package, which would be mounted with a reflow profile similar to that used for the device itself.


Figure 2. Close-up view of a solder ball engagement region of contact tips.
Click here to enlarge image

null


Figure 3. Close up of a loose contact gripping a solder ball on a BGA memory device.
Click here to enlarge image

Once mounted, the socket is ready to accept any device with the matching ball pattern. Package size can often vary from one supplier or die size to the next, so the socket keys in on the ball pattern. The contacts installed in the socket are designed so the solder ball on the device snaps into place between two beams that grip the solder ball (Figures 2 and 3). These high-frequency, dual-beam contacts hold the device in place during use, and allow the device to be unplugged and a new device inserted as needed. Figure 4 shows a cut-away view of the solder joint between the socket and the PCB.


Figure 4. Cut-away view of a contact gripping a solder ball on a device.
Click here to enlarge image

null

Individual Device Characterization

One basic application where this method is used is when the IC device is being tested or characterized. Figure 5 shows a test probe designed to mate with test equipment, where an individual device is plugged into the socket and performance measured against predicted outcomes. This step is important in the validation process, since it measures the actual performance of the silicon within the package. Several devices from a given lot or wafer can be analyzed, with the socket providing a quick and easy means for removal and replacement. The electrical performance of the socket is critical, since any signal degradation may hide or distort the device’s true performance.


Figure 5. Test probe for a single-device DDR memory BGA package. Courtesy of Agilent Technologies.
Click here to enlarge image

Ideally, the socket will be electrically transparent, and the device will perform as if it were soldered directly to the circuit board. Attention can be directed towards the module assembled with multiple devices with an understanding of the expected performance range from individual devices.

System-level Approach

Validation at the device level is not enough to ensure system-level performance. The signal path extends from the die to the package, then onto the module or system board. At each transition, there is an opportunity for parasitic effects to degrade the signal. The module board has become an intricately engineered circuit board, with precise routing and grounding patterns designed to successfully pass the variety of high-speed signals. If issues exist with one or more of the memory devices on the module, the entire module may fail. Likewise, an issue with the memory buffer or controller device may also cause failure. Even timing, impedance, or routing issues on the PCB can cause errors that are difficult to diagnose.


Figure 6. Fully buffered DIMM with sockets at all memory device positions.
Click here to enlarge image

Figure 6 shows a module populated with multiple individual device sockets. In this case, known good devices (KGDs) can be socketed to provide a segregated approach to analyzing other components of the assembly. Also, if one or more devices on the module are performing outside of tolerable guardbands, then those devices can be removed and replaced in seconds without the risk and trouble of rework. Figure 7 shows a similar module where the advanced memory buffer device is socketed to provide a high-frequency interface to the device that can be replaced quickly when a new version of silicon is available. In each case, the signal integrity of the socket provides a low-loss interface that performs as if the devices were actually soldered to the PCB.


Figure 7. Fully buffered DIMM with advanced memory buffer device socket in place.
Click here to enlarge image

The process and reflow profile used to solder the socket to the PCB is just as important when soldering a socket as it is when soldering a device. Insufficient solder paste or improper temperature profiles can result in open or cold joints, which may cause intermittent contact during use. Another item for future review is the number of insertions this type of socket can withstand. The nature of the contact to solder ball interface can result in slight grooving of the solder ball if the same device is inserted many times. This condition can result in high contact resistance or intermittent opens. The contact-to-solder-ball interface is sensitive to solder ball size. Packages from multiple suppliers may often exhibit solder ball size variation, or the JEDEC tolerance on a given package drawing can be wide enough to cause concern, which results in a standardized family of contacts which are refined to match actual ball size.

Conclusion

In general, the nature of how advanced packages are developed and assembled creates many hardships until all of the steps and components are validated. Until the point where the product and process are refined, the prospect of replacing a device without the use of a socket can add many days to the platform validation effort with rework fallout a high risk. Since the high-speed memory architecture has become such a vital part of the overall system architecture, a delay in memory validation or module availability can have enormous impacts to system-level validation efforts. Socketing critical components on the module can aid in the deployment of the modules, and give added benefit if the module becomes a critical path item for overall system validation.

Acknowledgements

The author would like to thank various customers for their contribution to this article, particularly Perry Keller of Agilent Technologies.

JAMES RATHBURN, founder and CEO, may be contacted at Gryphics Inc., 3850 Annapolis Lane, Suite 140, Plymouth, MN 55447; 763/509-0066; E-mail: jrathburn@gryphics.com.