Single-pass Assembly of SiPs
A Challenge to Multi-Chip Die Bonders
BY MANFRED GLANTSCHNIG, DATACON TECHNOLOGY
Increasing functionality of portable devices can only be managed through higher integration density of their functions. Combined with growing cost pressure and the need for short time-to-market, this calls for innovative solution approaches based on a combination of proven concepts and their systematic evolution. This includes, for example, the technology mix, modularity, autonomy, reusability, and precision.
The technology mix denotes the implementation of each function or subfunction in a particularly suitable technology; for example, MEMS for sensor tasks, CMOS for image signal processing, and GaAs for transceiver tasks in the GHz range. Modularity refers to the division of a function into logically coherent blocks, which can be freely combined to form new functionalities. Autonomy characterizes the completeness of the functional scope in the sense of a system or subsystem, while reusability of designs or components is an economical parameter for cost reduction.
Implementation Options: SoC vs. SiP
Higher integration density can be achieved in two ways: by integrating the functionality on a chip as a system-on-a-chip (SoC), or in a system-in-package (SiP). Strengths and weaknesses of both these implementation options are listed in Table 1.
Table 1. Some strengths and weaknesses of the highly integrated methods of SoCs and SiPs. (Source: TechSearch International Inc.)
As a fully integrated solution, SoCs are distinguished by high performance and reliability. The user only deals with one module, which contains all the functions and is fully tested; simplifying system design and procurement. However, the non-recurring expense (NRE) and the long development time are only worthwhile for high-volume applications. Furthermore, some functions cannot be optimized on a chip or can only be integrated at great expense.
SiPs allow alternative solutions. Implementing a function with previously developed and tested ICs is cheaper and can be ready for market within a short time, and can be vital to the short innovation cycle of modern consumer applications. The flexibility of different assembly methods makes it easier to combine heterogeneous technologies such as GaAs, standard CMOS, or MEMS. SiPs also allow functions to be standardized, which helps reduce costs.
In exchange for this, SiPs make other demands on development, procurement and production. Already in their design, different thermal, electrical, and mechanical problems must be considered. Moreover, the test strategy must ensure that the parts and semiconductor components used are fully functional known good dies (KGDs), because one built-in but defective part renders the entire SiP worthless. The procurement situation is more complex if packaged and unpackaged dies, and other components, come from different sources. Handling thin dies during the SiP manufacturing process is particularly demanding on the production facilities, which must ensure that they are not damaged during transport, feeding, assembly, and bonding. Suitable production facilities for SiPs must be flexible with the variety of existing possibilities and open to future extensions.
The SiP concept extends back to the primitive times of the hybrids, followed by multi-chip modules (MCMs), in which one or more ICs with active and passive components were situated on one level in horizontal integration. The next step of multi-die modules led to vertical integration through the stacking of multiple dies. Typical examples include stacked-die memory, which offered many times their capacity on the footprint of standard memory modules. This example shows the close interlinking and mutual enhancement of SoC and SiP concepts. Often, SiPs are forerunner versions of future SoCs available at short notice, whose increasing level of integration catches up through the scaling of the memory cells, and can replace them in the system.
The provisional end point of this development is complete SiPs, characterized by the vertical and horizontal integration of individual or multiple ICs with active, passive, and mechanical components through modern assembly methods with a functional scope previously found on typical system boards (Figure 1).
Figure 1. Typical application areas for SiPs.
Versatile Production Equipment
The diversity of components from all kinds of technologies used in SiP puts demands on the versatility of production devices. In one pass, they should be able to assemble all conceivable components, such as bare dies or packaged ICs; passive and active components; filters and adaptive networks; as well as mechanical parts, MEMS, and antennae. This single-pass assembly contributes to high yield, and thus to cost-effective SiP production. In contrast, SiP from multi-pass processes undergo an oven process several times, which stresses the substrate, requires additional handling steps, and reduces the yield. The economically expedient limit of the multi-pass processes with SiPs is around 3 chips. However, with single-pass assembly, the temperature profile of the oven process must be identical for all adhesives used.
Versatility for cost-effective, single-pass assembly of complex SiPs is provided by multi-chip die bonders. Based on the tried-and-tested 2200 apm+ bonder platform, a machine suited to SiP production was created*, which increases the flexibility, works economically, and has performance features for single-pass operation (Figure 2). Up to 25 wafers can be processed in a single cycle with automatic feed, the automatic tool changer can access 14 tool positions for pick-and-place, an ejection carousel has 5 ejectors, and a dispenser station separated from the mounting head increases the throughput up to 5000 cph. For large quantities, several multi-chip die bonders can be connected in series for higher throughput, supplemented with dispenser stations working in parallel, and linked via a transport system.
Figure 2. Flexibility of a multi-chip die bonder module for SiP production.
Absolute and Relative Precision
Obtaining the smallest possible package dimensions is key for SiPs, which can be achieved with a substrate layout with close tolerances. This requires high mounting precision from the bonder so that a positioning precision of ±10 µm at 3 σ is achieved at the tool tip of the bond system. For the axes of the separate dispenser station, on the other hand, ± 25 µm at 3 σ is sufficient (Figure 3). When bonding 2 stacked dies, 2 positioning variants are possible, depending on the bond topology. If both dies are bonded to the substrate, the top die must be aligned according to the substrate fiducial. If, on the other hand, the top die is bonded to the bottom one, then it must also be arranged relative to the bottom chip. This process is supported by digital cameras with CMOS sensors.
Figure 3. The integrated dispenser works in parallel with the bonder and increases throughput by up to 60%.
Direct Assembly and Flip Chip
Market researchers agree that the proportion of flip chip-assembled ICs in SiPs will increase in the next few years. Future-proof multi-chip die bonders can handle both assembly types: direct assembly and flip chip with the associated dipping station. This process step is influenced by the bonding techniques. Accompanying adhesives come either from a dispenser directly on the bond system, or from a separate dispenser system with its own drive and camera. For a criss-cross pattern measuring 2 × 2 mm, this requires just 0.5 seconds and is equipped with a touch sensor for the substrate height, whose measured values can automatically calibrate the height of the dosing needle and even out fluctuations in the substrate thickness. This precise setting is important for the assembly of small dies down to 250-µm edge length, for which even dots of adhesive measuring 250 µm can be set exactly. The same applies to controlling the BLT via the volume. Because fill layers often constitute part of the dielectric of adjusted lines, filter components and antennae, exact adherence to their thickness has an influence on the high-frequency characteristics of SiP components (Figure 4).
Figure 4. Exact adhesive application from a tiny dot to a surface pattern ensures a BLT for good HF characteristics.
Through parallel working of the dispenser and bond systems, the throughput for a SiP with two dies, for example, can be increased by 60%. Because the dispenser station can also be added on to existing machines later, there is the beneficial possibility of powering up a new production line with base station, upgrading it with the dispenser station as of a certain quantity, and then satisfying the increased demand cost-effectively with the higher throughput.
Hot Bonding Sheets
Because SiPs contribute significantly to electronics miniaturization, the application stipulates a maximum footprint and height, which is often guided by the thickness of the packaged ICs. So if a SiP consists of stacked dies, then these must be correspondingly thinner, and calls for special handling.
Thin chips are being assembled using bonding sheets, which can be cured at the same time as they are fitted using heated bonding tools and bonding support plates, whose target temperature can be programmed up to 350°C or 200°C. Low thermal capacitances ensure fast temperature rise and cooling for precise control of the curing process.
With a precision of ±10 µm at 3 σ and a throughput of up to 5000 cph, a new standard exists in machines for SiP manufacture in a single pass. Its cost efficiency should also help ensure accelerated market penetration by SiPs.
*2200 evo from Datacon
MANFRED GLANTSCHNIG, product manager, 2200 platform, may be contacted at Datacon Technology GmbH, Innstr. 16, A-6240 Radfeld/Tirol, Austria; 43/5337-600276; E-mail: email@example.com.