In the News
Survey Says: Semiconductor Packaging Materials Market to Hit $19.5B by 2010
SAN JOSE, CA - The semiconductor packaging materials market, including thermal interface materials (TIMs), is expected to grow from $12.0 billion in 2005 to $19.5 billion by 2010, claims the latest study from SEMI and TechSearch International, titled “Global Semiconductor Packaging Materials Outlook - 2005 Edition.” Laminate substrates, the largest market segment, were worth $4.2 billion worldwide in 2005, and are projected to grow at an 18% compound annual growth rate (CAGR) over the next 5 years.
The study’s findings are based on 130 in-depth interviews conducted with packaging subcontractors, semiconductor manufacturers, and materials suppliers. It includes data on revenue, unit shipments, and market shares for each packaging material segment; a 5-year (2006-2010) forecast of revenue and units, average selling price data, and trends; regional market trends analysis; and covers the implications of “green” manufacturing. The study also points out key opportunities for suppliers, including: increased supply of wire bond and flip chip substrates to alleviate the current supply imbalance; continued migration to smaller-diameter gold bonding wire technologies for cost reduction and super-fine-pitch bonding without wire sweep; substrates, die attach, liquid encapsulants, green mold compounds, and underfills that do not degrade moisture-sensitivity levels, and mix with low-k dielectrics and lead-free processing at a competitive price; and materials and processes for higher-pin-count wafer-level packaging, since this technology is expected to be used for DDR3 memory.
Applied Materials, IMEC To Research Nanometer Interconnect Processing Technology
SANTA CLARA, CA - Applied Materials and IMEC, a European independent nanoelectronics and nanotechnology research center, will join forces to develop 32- and 22-nm copper/low-k interconnect processing technologies using Applied Materials’ systems. They aim address manufacturing challenges chipmakers may face as they transition to future device generations, helping to bring products to market more rapidly while minimizing risk.
This joint effort lends itself to IMEC’s nanoelectronics research platform, which includes partners Infineon, Intel, Panasonic/Matsushita, Philips Semiconductors, Samsung, STMicroelectronics, Texas Instruments, and TSMC.
IMEC chose Applied Materials as an equipment provider for their core program on sub-45-nm CMOS research, which is being carried out in cooperation with IC manufacturers, said Dr. Luc Van Den Hove, VP of Silicon Process and Device Technology at IMEC. He added that the development program will build on Applied Materials’ integration knowledge in interconnect technology, especially in the areas of advanced low-k dielectrics and copper conductors. This new set of applied interconnect systems, will establish the capability for developing the sub-32-nm generation back-end process flow. “We expect to be collecting 32-nm data from this tool set by the end of 2006.” said Van Den Hove.
An alliance between IMEC and Applied Materials allows both organizations to use a broad range of interconnect technologies to develop integrated, high-performance 32-nm and below manufacturing processes said Farhad Moghadam, Ph.D., senior VP and general manager of Applied Materials’ Thin Films Group. In his opinion, this kind of collaboration is essential to understand the complex interface engineering and circuit scaling issues chipmakers will face with advanced technology nodes.
Intel Validates Working 45-nm Logic Chips
SANTA CLARA, CA - Intel has created the first fully functional static random access memory (SRAM) chips using its next-generation 45-nm process technology, paving the way to chip manufacture using 300-mm wafers by 2007. Intel also volume-produces semiconductors using 65-nm process technology, with two manufacturing facilities making 65-nm chips in Arizona and Oregon, and two more coming online this year in Ireland and Oregon.
300-mm wafer with 45-nm shuttle test chips.
“Intel has a long history of translating technology leaps into tangible benefits that people appreciate,” states Bill Holt, VP and general manager of Intel’s Technology and Manufacturing Group. “Our 45-nm technology will provide the foundation for delivering PCs with improved performance-per-watt that will enhance the user experience.” Intel’s 45-nm process technology also claims to allow chips with more than five times less leakage power than those made today, improving battery life for mobile devices and increasing opportunities for building smaller, more powerful platforms. The 45-nm SRAM chip has more than one billion transistors - though not intended as an Intel product, the SRAM claims to demonstrate technology performance, process yield, and chip reliability prior to ramping processors and other logic chips using the 45-nm manufacturing process.
Adding to the manufacturing capabilities of its D1D facility in Oregon, where the initial 45-nm development efforts are underway, Intel has announced two high-volume fabs under construction to manufacture chips using the 45-nm process technology: Fab 32 in Arizona and Fab 28 in Israel.
Henkel Restructures Sales, Names New VP of Sales and Marketing
Gordon Fischer, Ph.D.
IRVINE, CA - In efforts to enhance customer experience in the Americas, Henkel has put an Inside Technical Sales team in place to support its representative and distributor network, while also delivering direct access for customers. To expand its regional sales and customer service infrastructure and deliver personalized local support, Henkel recently enhanced its direct sales force by hiring leading industry representatives. The new Inside Technical Sales team adds another dimension to this sales network by providing technical assistance for inquiries regarding Henkel’s advanced electronics materials products. “In today’s climate of increasing time-to-market pressures and manufacturing challenges such as the lead-free transition, customers need quick and reliable product information from their suppliers,” comments Dave Edwards, Inside Technical Sales supervisor for the Electronics Group of Henkel.
In other news, the Electronics Group of Henkel appointed Gordon Fischer, Ph.D., to VP of sales, marketing, and technical services for the Americas. In this position, Fischer will lead the Americas sales team, manage the company’s marketing plan, and direct the technical service infrastructure for Henkel’s semiconductor and PCBA products. Among Fischer’s goals in this new position are the continued expansion of Henkel’s presence among OEM and EMS firms, sharing lead-free research and process knowledge with customers, and promoting the company’s approach to materials-set development for the semiconductor packaging market. Fischer previously held the position of global director of product management for the company’s semiconductor business, and has 15 years of experience in the industry. He has held several R&D positions throughout this professional career with such companies as Dow Corning and Rohm and Haas.
NuSil Grows EPM Line
CARPENTERIA, CA - NuSil Technology has expanded its line of electronic packaging materials (EPMs), in which all included materials will have low outgassing properties to prevent contamination. NuSil’s EPMs have undergone extensive processing and maintain weight losses of less than 1% after exposure to temperatures exceeding 275°C for one hour. The revamped offering includes potting and encapsulating materials; static-dissipative and glop top materials; dielectric gels; and TIMs in grease, adhesive, and gel forms.
Karnezos Joins SunSil Advisory Board
Marcos Karnezos, Ph.D.
ALAMO, CA - Marcos Karnezos, Ph.D., whose semiconductor industry experience exceeds 26 years, has joined the advisory board of Silicon Valley-based SunSil Inc., an international technical sales and marketing organization. SunSil represents companies in the wafer processing, assembly, and test sectors of the semiconductor industry. Karnezos, who holds a doctorate in physics, was most recently special technology advisor to STATS ChipPAC. Previously, he served as VP of technology at both ASAT and Signetics KP.
Unaxis Appoints New Division Head
Peter Podesser, Ph.D.
ST. PETERSBURG, FL - Coming from Schärding, Austria-based EV Group (EVG), where he served as the company’s CEO for the past 5 years, Peter Podesser, Ph. D., has been appointed Division Head of Unaxis Wafer Processing, succeeding Bob Kase, who retired at the end of 2005. Before EVG, he held various management posts in Europe and Asia at Austrian technology company RHI AG over a 10-year period. He earned his doctorate in Social and Economics Science at Vienna University of Economics and Business Administration.
Southwest Electronics Production Exposition Announced
DALLAS, TX - When Jerry Cupples and Jim Baker, officers of the Dallas SMTA Chapter, learned that 2006 NEPCON Texas was “indefinitely postponed” by Reed Exhibitions, they took matters into their own hands. They formed the Texas Technical Exposition and are launching the Southwest Electronics Production Exposition (SWEPEX), to be held November 14-16, 2006, at the Plano Center in Plano, TX. The show will feature conferences and technical sessions by industry experts, and will target exhibitors from the semiconductor modules, defense and aerospace electronics, medical, optical networking, and telecom operations.
Cupples says there is a 3-year plan to establish this as an annual event, and to prove that a “right-sized” exhibition of production equipment and services will be beneficial to both attendees and exhibitors in the region. It will be organized on a “regional” basis, not a “local” basis, attracting attendees from nearby cities throughout the southwest. For more information, please visit www.swepex.org.
Agilent Chosen to Provide Testers for Nanotechnology Program
PALO ALTO, CA - The Crolles2 Alliance, which teams STMicroelectronics, Philips, and Freescale Semiconductor together in efforts to develop test software and hardware for nanotechnology engineering and industrial applications, has purchased three Agilent Technologies 93000 pin-scale testers and four 4073 advanced parametric testers for research, development, and industrialization of CMOS process technologies.
The Alliance and Agilent will embark on a joint development program (JDP), in which they will collaborate closely to develop engineering tools for R&D and production, focusing primarily on memory and mixed-signal device test. In exchange, the Alliance will provide access to test-related technology in both industrial and engineering environments. The Alliance’s center in Crolles, France, includes a 300-mm wafer plant, currently in production at 90-nm technology. The Alliance also has a pilot line for 65-nm technology, as well as developments in process for 45-nm and plans for 32-nm technologies.
SEMI Issues 14 New Technical Standards
SAN JOSE, CA - Applicable to semiconductor, flat-panel display (FPD), and MEMS manufacturing, SEMI’s 14 new standards were developed by technical experts from equipment suppliers, device manufacturers, and other companies participating in the SEMI International Standards Program.
The standards include a specification for round, 200-mm polished monocrystalline gallium arsenide wafers, a test method for determination of particulate contamination from mini-environments, and a specification for job-deck data format for variable shaped beam (VSB) mask writers.
“These new specifications, which include several applicable to the emerging growth area of compound semiconductors, will help reduce the industry’s manufacturing costs and speed time-to-market,” said Bettina Weiss, SEMI director of International Standards.
The new standards join more than 720 standards that have been published by SEMI during the past 32 years. About 1,100 volunteers worldwide participate in the SEMI Standards Program, which was established in 1973 and is made up of 17 global technical committees. SEMI Standards cover all aspects of semiconductor process equipment and materials, and are published three times a year. Visit www.semi.org/standards for further details.