Streamlined Thermal Modeling


Reduces Time-to-Market

By Andy Manning, Flomerics Inc. and Mark Hemmeyer, NVIDIA

As part of integrating media and communications processors (MCPs) into their products, personal computer original equipment manufacturers (OEMs), system builders, and motherboard manufacturers must ensure that these high-performance chips’ power is properly dissipated to maintain die temperatures at, or below, thermal specifications. A “turn-of-the-crank” process has been developed for optimizing package selection for new processes and developing reference thermal solutions. This process uses compact models to replicate the thermal performance of a new part in a particular package in less time than traditional methods (Figure 1).

Figure 1. The top and bottom of a high-performance chip.
Click here to enlarge image


Evaluating New Chip Thermal Performance

The process of optimizing the package, and developing a thermal reference design, was used in the development of a new MCP family.* Manufacturers of products that use MCPs need to be concerned about maintaining die temperatures at or below thermal specifications to ensure the proper functionality, performance, and reliability of the chip. To assist them, one MCP manufacturer** evaluates the thermal performance of new products in multiple alternative packages to determine which provides the best thermal performance under the widest possible range of conditions. In most cases, several reference designs are developed that can be used to produce a mechanical design to meet thermal performance requirements. Systems builders are provided an accurate thermal model of their part to be imported into a thermal simulation of the complete system, making it easy to determine how the part contributes to, and is affected by, overall thermal performance of the system.

The process of evaluating thermal performance of a new MCP used to be a much longer and more expensive process, and provided less information to systems designers. Evaluating the effect of different packages on the thermal performance of a new chip has long been achieved by building a prototype of the package and chip, and performing physical testing. This means thermal performance evaluations cannot be initiated until prototypes are available, which sometimes delays the product introduction, and nearly always limits the ability to optimize thermal performance by considering alternative packages.

Case Study: Compact Model Saves Time

A number of years ago, thermal simulation software*** became available, making it possible to produce detailed models which reconstruct the physical geometry of the package, and accurately predict the temperature of various elements within the package for a variety of conditions. But maintaining the accuracy of the simulation required an intricate manual process that involved replicating the geometry of the die and package, as well as lengthy simulations related to the complexity of the chip geometry.

Recently, a new process was developed that reduces the amount of time required to simulate thermal performance of new products. The new process takes advantage of the 2-resistor and Delphi compact modeling methods, which make it possible to quickly produce a computationally efficient representation of a component’s thermal characteristics. A compact model is not constructed to mimic the geometry and material properties of the actual component. Rather, it is an abstraction of the response of the component to various boundary conditions, such as flows, temperatures, and pressures. Die size, heat dissipation, and package characteristics - such as substrate size and number of balls - are entered on a web form, which generates and displays a compact thermal model that predicts the temperature of the various elements within the package accurately, regardless of the computational environment in which it is placed.

For a typical version of the new MCP, a number of different packages are evaluated, with the goal of optimizing the design by trading off thermal performance against package size. The thermal performance of each alternative package can be defined and modeled in an hour’s time, because instead of defining the detailed geometry of the package, a few parameters are entered. The models themselves provide basic thermal performance parameters under JEDEC standard boundary conditions. This process used to take at least a week when modeling the full geometry of the package and die. The new approach makes it possible to do a thorough thermal performance evaluation well in advance of first silicon. Only minimal physical testing is required to confirm the accuracy of the simulation during the time-sensitive later stages of the development cycle. In this case, a ball grid array with 31 × 31 balls was determined to provide the best performance (Figure 2).

Figure 2. Composite picture of a chip showing temperature simulation (left side) and the chip’s regular colors (right side).
Click here to enlarge image


Thermal Design Guide

A detailed thermal design guide is needed to streamline the design process, allowing users to focus their resources on higher-level systems design issues. The design guide provides answers to questions such as whether or not a heatsink is required under certain ambient temperature and airflow conditions, and what type of heatsink provides the best performance. To obtain this type of detailed thermal performance information, 2-resistor and Delphi compact models for the final package are downloaded from the website and imported into the thermal simulation software. In the thermal simulation environment, various reference mechanical designs based on chips’ target market - in this case, high-end desktop systems - were developed.

A key goal was to accurately define the conditions under which a heatsink is or is not required. Whether or not to use a heatsink is an important decision because heatsinks typically add 50 cents to $5.00 to the bill of materials. On the other hand, avoiding a heatsink often requires maintaining a specific volume of air flow, which may in some cases require a higher-performance fan. System designers are in the best position to make this kind of tradeoff, so an engineer’s goal is to provide detailed and accurate information that they can use to optimize their mechanical design. The thermal simulation software provides the freedom to evaluate the product in the chosen package under any thermal conditions. In this case, different heatsink geometries, thermal interface materials, and airflow conditions were tried. The time needed to perform these evaluations was reduced by obtaining standard models of heatsinks, thermal interface materials, fans, and other components from the website.


Thermal simulation allows engineers to play with various environments, such as looking at the impact on junction temperatures as the airflow across the chip is reduced. In the case of the new MCP, a number of different active and passive heatsinks were evaluated and one that provided the best performance was chosen from each category. The chip was evaluated under different operating speeds, airflows, and board conditions with no heatsink, a passive heatsink, and an active heatsink. Upon completion, a detailed engineering document was provided that makes clear what is required to keep the chip cool under a wide range of conditions. This information enables engineers to make decisions in the early stages of their design process, such as whether to work on improving the airflow over the chip or to use a heatsink. When prototypes are received, testing showed that the simulations had achieved the usual accuracy levels of 5 to 10%. Validated compact models of the chip can be provided that plug into any system-level thermal models, getting products to market faster.

*NVidia nForceTM4 media and communications processors
***Flotherm software from Flomerics Inc.

ANDY MANNING, Ph. D., VP of thermal engineering, may be contacted at Flomerics Inc., 4 Mount Royal Ave., Suite 450, Marlborough, MA 01752; 508/357-2012; E-mail:; MARK HEMMEYER, mechanical engineer, may be contacted at NVIDIA, 2701 San Tomas Expressway, Santa Clara, CA 95050; 408/486 2000; E-mail:

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