3D integration in packages involves stacking two or more planar devices, increasing their capability as the vertical grows, much like the old-fashioned game of checkers. However, with stacked chips or packages the connection between levels must be strong. It’s not that wire and flip-chip bonding have lost favor, but there exists a simpler, more elegant method of connecting wafer-to-wafer or die-to-wafer directly using through silicon vias (TSVs), thus shortening connections.
For a long time, wafer fabs and semiconductor assembly and test (SATs) providers have looked at 3D as a way to make smaller packages with more functionality. Challenges seem to evolve from alignment, deep silicon etching, and perfection of the metallization lining of the etched via. If the Bosch gas switched process is used for etching deep silicon, a bumpy, wall emerges. If a laser is used for via drilling, other problems arise. Then the etched hole is lined with dielectric and deposited with seed metal in preparation for electroplating.
Early in 2007, IBM announced that it developed a way to incorporate TSVs into chips that shortens the distances for data to travel by 1000×. Since their introduction, other companies began talking 3D.
Both 3D chips and MEMS sensors have been using the deep reactive ion etching (DRIE) etching process, commonly known as the Bosch process. The biggest question seems to be whether it should be performed before or after wafer thinning?
The via-first approach, developed by the EMC3D Consortium, applies to thick wafers; whereas the via-last technique is used for thinned wafers. When using the via-last approach, the DRIE application becomes a challenge. Handling and chucking silicon-on-glass wafers can be difficult, especially when controlling warp. In a recent presentation given at SEMICON Europa, Michel Puech of Alcatel Micro Machining Systems talked about a specific chuck and clamping system for via-last applications using a series of small edge tips on the edge-exclusion area of the wafer periphery to compensate for warping of stacked wafers.
There are lots of bumps along the way for 3D. Perhaps the most costly is the time required to etch using the Bosch process. TSV etching takes time, therefore productivity becomes the issue. Also, there are many types of drilling, including DRIE systems. David Haynes, Ph.D., of Surface Technology Systems, (STS) discussed his firm’s DRIE during an Advanced Packaging-based MEMS webinar (www.apmag.com).
The MEMS market has a predicted CAGR growth rate of 13%, up to $10 billion by 2010 according to Yole Développement’s figures. Though MEMS has finally gone mainstream, 3D remains in the active arena where companies are establishing their expertise. In the next few months, Advanced Packaging will present a three-part webcast series sponsored by EV Group. Look for the announcements on our website as well as in the issue.
It’s time to gather as much knowledge as you can about this enabling technology. In an industry where knowledge is power, it’s good to be the king.