SATS Update: Riding the Packaging Wave



Semiconductor assembly and test service (SATS) providers have been all over the news this year, with mergers and acquisitions, R&D collaborations, and technology innovations. Here‘s what representatives from Amkor, STATS ChipPAC, Unisem Group, and PSi Technologies had to say about some of the big issues.

The tides of semiconductor technology are turning, with much of the focus shifting to back-end assembly and test. According to research reported by Gartner Dataquest, the packaging industry is growing faster than the semiconductor industry as a whole, due to the increasing relative value of packaging to semiconductor products.1 As flip chip goes mainstream, through silicon vias (TSVs) enter production, and front-end fabs add wafer-level packaging technologies to their service portfolio, the effect all this has on SATS providers deserves a close look.

Market Drivers

Today’s consumers demand products optimized to their specific and ever-changing use requirements, which drive increased convergence of computer, communication, and entertainment functions, says Christopher Scanlon, V.P. corporate research & development, Amkor. “Amkor is seeing strong demand for system-in-package (SiP) and 3D packaging technologies that enable flexibility and customization for high levels of semiconductor integration against shorter time-to-market and product life cycle constraints,” he explained.

Bruno Guilmart, CEO of Unisem Group agrees, noting that what has changed in the electronics industry is that rather than being enterprise driven, it’s consumer driven. One differentiator for Unisem from other SATS companies is the automotive market, which accounts for 25% of the company’s business. While the number of cars isn’t actually growing, the electronic content is growing, he explained, and none of their competitors seem to be focused on it, making it an ideal growth market for Unisem. Guilmart said the company has launched a zero defect initiative, and a six sigma program as a push towards quality. While that’s not unusual from a wafer fab perspective, it’s somewhat of a novelty for a SATS provider, he said.

Figure 1. A die bonder picks die from wafer and mounts it onto a high density leadframe. (Courtesy of Amkor.)
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Technology Drivers
Has the transition from wire bonding to flip chip and other wafer-level interconnects really begun? Amkor, identified as one of the top five SATS providers in the industry by revenue, believes it has, and is positioning itself accordingly. “Amkor has invested heavily in leading edge flip chip and wafer-level processes, with their supporting advanced assembly and test capabilities,” said Scanlon.

Figure 2. This saw-and-pick machine processes laminate-based packages. (courtesy of Amkor).
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Another member of the “top five,” STATS ChipPAC has also strategically invested in next-generation integration technology. According to Tan Lay Koon, CEO and president, STATS ChipPAC, the company is moving forward with developing wafer-level 3D integration solutions such as TSVs and microbump bonding for three dimensional (3D) die, silicon-substrate-based packaging solutions, and embedded active die technology.

Unisem Group, whose main focus is fine-pitch BGA, pin-grid arrays (PGAs), and QFN packages, sees the growing trend for its customers as the integration of multichips into some form of module or stacked-die package. “We talked a lot in the late ’90s and early 2000s about system-on-silicon,” said Guilmart. “That really hasn’t happened in the industry because there are a lot of challenges of doing that on silicon; it’s a lot more practical to do it in a package.”

As he discussed trends in 3D stacking in his presentation at SEMICON Europa 2007, Eric Mounier, Ph.D., cofounder of Yole Dévelopment, suggested that rather than transitioning to newer interconnect methods, it’s more likely that all the technologies will co-exist, and be application specific. The higher the density and functionality levels, the more sophisticated the technology.

Front-end Fabs vs. SATS Providers vs. EMS Providers

As 3D wafer-level packaging (WLP) edges its way to production, industry experts speculate whether foundries will upend traditional roles by pulling packaging and test processes in-house. For example, Taiwan Semiconductor (TSMC), a pure foundry, announced a 12" WLP facility to perform design, package, and test services previously outsourced to assembly houses.2 Guilmart doesn’t see this as a viable concern. “I come from a wafer fab background, so I’ve had the chance to look at this from both sides.” He explained. “You talk about bumping to a wafer fab manager and it’s pretty scary for him because this is considered a ‘dirty’ process.”

Scanlon concurs with Guilmart. “Wafer bumping and thick dielectric/copper wafer-level redistribution processes are not a good technical or ROI fit for high cost/sq. ft. wafer fab facilities.” Instead, Scanlon predicts that the growth in flip chip, WLP and emergence of TSVs for 3D integration will drive more collaboration between foundries and SATS providers.

Although it appears that packaging houses will compete with fabs for the WLP business, its Koon’s opinion that logical hand-off points will continue to exist where the fab role ends and packaging begins. This is because the tool set used for WLP processes is typically different from that found in a wafer fab. Ball-attach and end-of-line processes such as singulation, mark, and pack clearly do not fit the current fab model, he noted.

Figure 3. This Load board was designed to test RF devices. (Courtesy of STATS ChipPAC)
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But where, exactly, is that line between the front and back ends? At one time, it was consider to be at the dicing stage. But all that has changed since more packaging processes occur at the wafer level. Guilmart agrees that the line has blurred between what could be defined as the wafer fab domain and the assembly and test domain. For instance, packages didn’t used to be part of the design process as much as they are now. Now, the package has to be designed along with the IC. He added that it’s also not customary to see testers in a wafer fab. The focus for wafer fabs today is development of 300-mm wafers, which is very labor intensive. “I’m not sure they have the time, money, or desire to look into more assembly-related technologies,” he noted.

Koon sees the hand-off point shifting going forward. In the case of through silicon via (TSV) technology, if “via-first” TSV is embraced by the fab industry overall, then fully processed wafers with buried vias would be the hand-off point, he explained. The packaging industry would develop the processes for grinding the silicon to expose the vias and process them for subsequent “via-last” TSV interconnection. “The ‘via-last’ TSV interconnection enables multiple functional blocks to be combined using the same technique to achieve logic and memory combination,” he said. “Such integration capability is the unique role of the packaging industry. Back-end providers can bring together wafers from different fabs for integration with ease and clearly this does not compete with the front end in the same segment.”

Interestingly enough, Mounier included Amkor among Yole Développment’s list of major players in the development of stacked Flash memory technologies - mostly IDMs like Samsung, Toshiba, Intel, and Micron. “It’s quite impressive to see them here,” he said, “because they are a back-end company.”

For companies like PSi Technologies, a company that specializes in assembly, test, and packaging for power semiconductors, there is less concern that they will eventually be competing with the front-end fabs. “The products we assemble require packaging that must effectively facilitate high thermal dissipation in the device, for example, heatsinks,” noted Freddie Canlas, director, marketing and sales PSi Technologies, Inc.

At the other end of the spectrum is the question of competition between SATS and EMS providers for SiP assembly. The general view among SATS providers is that they will dominate. “Board stuffing and assembly and test are two different animals,” said Guilmart. SiPs with multi die requiring encapsulation need cleanroom capabilities, something EMS providers don’t tend to have. Scanlon agrees, adding that as long as SiP technology continues to leverage advanced interconnect technologies, the tasks will fall to the SATS providers. However, Koon noted that EMS companies will have a place in the industry with less complex SiP packages that use direct chip attach (DCA) or pre-packaged ICs in combination with SMT components.

Mergers, Acquisitions and Joint Ventures

As more customers seek turnkey solutions, SATS providers are stepping up to the plate, expanding their offerings. “We’re seeing an increase in the overall percentage of the volume that we test vs. the volume we assemble.” noted Guilmart. “The primary motivation is supply chain optimization.” Unisem recently completed the acquisition of Advanced Interconnect Technologies (AIT), forming Unisem Group. “We had very little customer overlap - a great opportunity of cross-selling for us,” said Guilmart. “We also had a lot of complementary technologies from a packaging perspective.” Unisem’s strength is in small footprint QFN, while AIT brings expertise in BGAs and large-footprint QFN packages. He explained that the industry is still extremely fragmented, so further consolidation is expected. Unisem will continue to look for acquisitions as a way to expand their product offerings. “It’s a build versus buy decision,” he said. “We’ll always look for acquisitions as we move along.”

Figure 4. Operators programming wire bonders in Korea factory. (Courtesy of Stats ChipPAC)
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Another way SATS providers are achieving this is through joint ventures. For example, in May, 2007, Amkor and UTAC, another top 5 SATS provider, entered into a multi-year cross-license agreement wherein UTAC adopts Amkor’s MLF technology and Amkor uses UTAC’s QFN patents. The deal reportedly covers IP rights, and transfer of associated packaging technologies. Amkor has entered into such agreements before, such as with STATS before it was STATS chipPAC, often at the request of a customer. The agreements create legal environments where packages can be distributed more freely without infringements.

“Pooling of resources and the desire to be at a size big enough to leverage these resources are the main drivers for these joint ventures,” said Canlas, “As a public company, we (PSi Technologies) are always open to all financially viable business options, including joint ventures.”

Guilmart noted that collaboration allows for leveraging the cost of developing technology with multiple partners. “That’s the trend,” he said. “Whether it’s in the foundry space or the assembly and test space - obviously we’ll try as much we can to leverage the cost of developing technology.”

Strategic Positioning

Statistics show that SATS providers have been gaining market share of worldwide assembly and test, and are expected to have 50% of the market by 2010. Canlas says IDMs would rather spend their investments on their core competency, which is product and wafer design as opposed to assembly and test. Assembly and test is the core competency of SATS providers.

The consolidation of the industry is driving more demand for outsourcing to SATS providers to reduce internal manufacturing cost and supply chain risks, explained Koon.

Scanlon predicts the percentage of outsourced assembly and test will continue to increase as semiconductor companies focus their capital investments on their core competencies and rely on SATS providers to develop a broad range of advanced packaging technologies.


It seems the greatest challenge facing the SATS industry is going to be figuring out how to handle the growth spurt. Strategic positioning, such as putting capacity in place for specific customers rather than randomly building factories and hoping the business they attract will fill them up, is a growing trend.3 Identifying key differentiators will help the smaller players stay in the game. Investing in emerging technologies and partnering with complementary service providers will help the front runners maintain their competitive edge. And while the point of hand-off continues to fluctuate, it’s clear that SATS providers will be critical to the future success of the industry.


1, 3. This Week in Packaging, Jeffrey C. Demmin, AP Semi-monthly, October 3, 2007

2. 3D: Is the Best Yet To Come? George Riley, Ph.D., Advanced Packaging, Volume 16, Issue 7, p. 44

Tracking Growth in Packaging, Assembly, and Test

Global packaging, assembly, and testing (PAT) revenues are expected to grow at half the rate in 2007 that they did in 2006, and will improve marginally in 2008, according to new data from Gartner Dataquest. A closer look inside the numbers reveals the emergence of outsourced semiconductor assembly and test services (SATS), which is poised to balloon by nearly a third over the next three years and reach equal footing with IDMs.

In 2008, Gartner sees a 12% increase in total worldwide PAT sales to $54.15 billion, followed by another minor slowdown to 9% growth in 2009 ($59.12 billion). SATS, meanwhile, will enjoy nearly 17% growth next year (to $24.53 billion) and 13% in 2009 (to $27.72 billion).

The outsourced services segment has been growing at least 50% faster than the semiconductor industry overall since 2001 - last year SATS surged 26.4% vs. just 8%-9% for the total semiconductor industry, according to Jim Walker, research VP for Gartner’s semiconductor manufacturing and design research group. IDMs are outsourcing more, he pointed out, largely because of the trend toward customization, which can be difficult to cost-efficiently digest because equipment sets are too expensive, and utilization rates are lower.

At the forefront of the outsourcing growth trend is the test segment, expected to surpass IDM sales by 2010. This is noteworthy, Walker points out, because sensitive in-house processes could be deduced and duplicated by gleaning information about yields and test vectors. Still, “because of capitalization issues, test is being outsourced more and more,” he noted.

Figure 1. Global PAT and SATS Forecast, 2007-2011
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The value of semiconductor packaging has been steadily increasing in relation to total semiconductors - from 15% to around 20% in the next 4-5 years, Walker noted. Part of that is due to enabling integration on the package instead of the die, which helps manufacturers more quickly and cost-effectively squeeze through the market windows shrunk by “have it your way” consumer product demand. This integration essentially means “taking chips off the shelf and making a system-on-chip without the non-recurring engineering costs,” explained Walker. In effect “we’re integrating Moore’s Law via packaging.”

Also a factor in the growing importance of packaging is the change from leadframe to substrate-based packages. Increased costs for more expensive raw materials are being passed along, increasing the packaging value, Walker noted. In addition, packaging is now being done in conjunction with silicon - DDR2, DDR3, and DDR4 packaging has electrical properties that affect silicon speeds, so the packaging side can dictate what the substrate is for the module, what the packaging type is, etc.

Like the rest of the industry, SATS firms had a soft 1Q07, and particularly in April when their capacity utilization bottomed out, Walker noted. But capacity is now back up to the mid-80% range, “not tight, but over breakeven,” he said. And unlike other sectors of the chip world, PAT companies have become disciplined at managing their equipment and capital assets in the past couple of years.

Walker is a bit optimistic about the remainder of 2H07, noting news from earlier this year about increased shifts to outsourcing (e.g. LSI Logic using STATS ChipPAC). He’s also optimistic about the start of 2008 as well, citing major consumer-spending factors such as the 2008 Olympic Games and the US presidential election.

James Montgomery, News Editor, Solid State Technology