Issue



Correct-by-construction Methodology Enables Consumer Electronics Designs


09/01/2007







The Japanese market, with its focus on consumer electronics and telecommunications, has embraced chip/package co-design and optimization for wire-bonded and system-in-package (SiP) devices. The methodology is gaining widespread adoption because it’s helping to bridge the gap between the design of high-performance chips, their packages, and the rest of the system.

Japanese design teams have turned to a chip/package, correct-by-construction methodology to reduce re-spins of chips and packages with greater success, and many have taken the designs through to silicon. They have implemented it on wire-bonded SiP and package-on-package (PoP) designs, saying that it offers significant flexibility. Therefore, the methodology allows consumer electronics companies the ability to respond quickly to market changes.

Increased adoption of this new mode of design should not be a surprise, because consumer electronics and telecommunication segments have exacting and unyielding requirements, where even a minor cost overrun on product development is the difference between success and failure. The need to make the time-to-market window is equally critical when success or failure depends upon meeting an unmovable deadline, such as Christmas, or hitting another all-important market opportunity.

The ability to optimize the I/O plan for SiP and PoP design simultaneously has proven to be a key strategic weapon for success. Chip/package co-design is becoming an essential ingredient for developing an SiP or PoP product design architecture or platform that can span multiple price points; saving money by leveraging higher-volume pricing along the way.

Using an interconnect synthesis approach, the methodology is able to analyze a wide range of variables to converge on a final I/O plan. With its embedded chip/package extraction, and estimation and simulation capabilities for signal/power integrity, the impact on electrical performance is addressed before final implementation.

The methodology can assist design teams in determining package escape, routability, and parasitics for simultaneous tradeoffs between chip and package design. They’ve found that prototyping using this methodology is an effective way to predict chip/package cost and complexity estimates accurately when responding to request for quotes (RFQs). What’s more, it eliminates the need for imprecise and impractical spreadsheets to manage I/O sequencing because it automatically inserts cells during initial cell instantiation.

As the design progresses, the methodology can be used when there are changes in the chip or package design to validate the initial strategy or to re-optimize the I/O plan with an updated set of design criteria. Moving forward, the same product design architecture can support upgrades as well, because the initial design was developed with consideration for planned upgrades.

So many of today’s design considerations are determined by budget. In another example of cost control, this methodology offers design teams the ability to perform chip-to-chip I/O planning for either stacked or side-by-side SiPs. This methodology helps save money by maximizing the amount of direct chip-to-chip bonding by sequencing I/Os on one chip in the context of the other chip. I/O planning also helps maximize the use of single-layer package routing to save costs and reduce budgets.

With PoP, where packaged chips are stacked on top of one another like a club sandwich, the methodology’s ability to simultaneously support multiple domains is essential. Successful implementation of this emerging technology hinges on the ability to plan and implement an I/O optimization strategy. This strategy must consider all chips and all packages in the stack together as a single-system interconnect, and not as individual entities.

Design reuse is also an area where design teams can save money. In this scenario, when new chips arrive, the I/O plan for these new chips needs to be driven from the package up to the chip to make sure that the design team can reuse the existing package, saving time and money.

All of these design strategies can only be done by introducing a correct-by-construction, co-design, and optimization methodology into the design flow, but it does not turn chip designers into packaging experts. Instead, it enables packaging guidance early in the design flow to help them meet product goals. Japanese designers have found that this methodology reduces costs and time-to-market, while offering flexibility for last-minute changes and helping improve die and package design.

Japan, long known for its innovative management style, has once again embraced a new methodology that will enable the flexibility and agility to deliver products to meet consumer demands on time and within budget.


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KAUSHIK SHETH, CEO, may be contacted at Rio Design Automation, 2901 Tasman Dr. Ste., Santa Clara, CA; 408/844-8038 x11; E-mail: ksheth@rio-da.com.