Integrating Thermal Management and Burn-in Operations
Thermal Dissipation and Power Variance Prevention
In the semiconductor industry challenges appear to be directly related to Moore’s Law. In reality the culprit is consumer demand for more functionality, faster speeds, and smaller features. Technically, the integrated circuit (IC) industry is progressing at a rate that’s unmatched by any other industry. Yet, moving forward, it faces technical hurdles that slow progress, and must create advanced solutions without increasing costs.
For instance, the industry-wide movement to finer wafer-fabrication architecture and smaller node sizes has created a new set of problems at the back end that must be addressed. Specifically, smaller transistors and fabrication architecture have created a problem related to current leakage and device power. As we move through 90-nm processing and into the 65-nm area and beyond, current leakage becomes increasingly troubling. Semiconductor dielectrics cannot withstand the combination of decreased node sizes and subsequently thinner dielectric thicknesses. The thinner dielectric layers are allowing leakage to seep through at inconsistent rates.
Leakage rates vary from devices coming off of the same wafer that are fabricated right next to one another. Leakage, and the resulting device power, has been a source of increasing costs for IC suppliers due to the requirements necessary for management of the escalating thermal values and disparities (Table 1). Historically, IC designers, packaging engineers, test engineers, and burn-in engineers did not collaborate on projects from the early stages through production, instead following the traditional “over the wall” project management methodology which creates obstacles generated upstream and left to be managed downstream. However, the introduction of current leakage, device powers, and power disparities demand a higher level of collaboration for long-term success.
Figure 1. Burn-in operations at reduced process nodes exhibit a higher percentage in power variation.
The burn-in operation is being affected by the resulting thermal properties of latest-generation devices. In the burn-in operation, a device is stressed through the introduction of an applied voltage and increased ambient environment temperature. The objective of a burn-in sequence is to screen out weak devices and drive an infant mortality to those devices that do not possess the robust infrastructure required to exhibit in-field reliability.
Figure 2. 90-nm device temperatures in a burn-in chamber as ambient temperatures increase.
When a burn-in sequence is defined at a specific voltage and that voltage is applied to the device, leakage occurs. Leakage creates heat. Heat creates resistance. When a burn-in system identifies an increase in resistance, it applies more current to maintain a specified voltage, V=IR. As more current is applied, more current leaks out of the device. As more current leaks out of the device, more heat is generated. If not properly managed, these devices will go into thermal runaway and burn up. However, if all devices had equivalent leakage rates, a heatsink can be applied to interact with the ambient airflow and pull heat from the device, creating stability (Figure 1).
Table 1. Gate dielectric leakage rates have been on the rise since 2005, and is expected to continue increasing as gate lengths reduce. (IRTS Roadmap 2006-07 update)
Devices that do not exhibit leakage can be processed by using a defined ambient temperature, which is calculated to bring the junction (die) temperature of the device to the desired target range. Generally, these values range between 125°C and 150°C. Maintaining all the devices within a specified temperature range is a challenge if some devices experience leakage, and thus heat up during the process, and others do not. In this case, if the ambient is set at one temperature, some devices will be properly burned in and others will not.
These problems become prominent over a wider range of semiconductors at the 90-nm feature set. During the early stages, burn-in operations identified the problems and determined that devices would be binned (or batched) based on power ranges. This allowed burn-in operations to process devices that exhibited similar power-dissipation rates, and meant that the burn-in engineer could process each lot at different chamber set points, one for each bin (Figure 2).
More capabilities and higher performance in 90-nm devices and the movement to 65-nm processing has resulted in leakage rates that vary in wafer batches by as much as ±50% and higher. A device that is designed to run at 6W will have devices in the lots that experience power dissipation rates from 3 to 9W. Binning reduces equipment efficiency and throughput. The equipment is set to run a specific sub lot of a device run, hence making the system incapable of processing any other device. At this point, the IC supplier is not getting full entitlement of the equipment.
Figure 3. 90-nm device temperatures using an integrated thermal management solution in an existing burn-in chamber.
The increase in thermal variances, due to leakage, has created a demand for advanced thermal-management solutions in burn-in operations. As the amount of bins required to effectively process devices has increased, and the costs have outweighed the justification, there has been a need for back-end operations to explore more effective ways of managing burn-in processes and operations. Changing the way things are done could be seen as demand for new equipment, which requires capital expenditure. Additionally, as the industry has evolved, new devices that are now experiencing thermal issues are those that already have a set cost structure for the systems in which they were intended, and would require an increased cost for a similar product that has a few more features and is slightly smaller. An IC supplier is not likely to invest in a new piece of equipment that has lower capacity rates and consume the costs. So, IC manufacturers are challenged with processing devices with minimal cost increases and, most importantly, requiring a solution with a lower cost-of-ownership than a new piece of equipment.
There are solutions that leverage existing burn-in systems, enhancing a system’s capability to thermally manage a device independently inside a burn-in chamber. These use a combination of heatsinks, heaters, sensors and electronic circuitry that manage to balance the device temperatures throughout a fully loaded burn-in system. Sensors monitor device temperatures; heatsinks pull heat from devices; the circuitry reads and reacts to the device temperature by cycling the individual device heaters on and off. These aftermarket solutions are designed to integrate with existing systems, extending the life of existing chambers (Figure 3).
Higher power devices, in conjunction with the effects associated with leakage, have exposed a subset of issues that define the limits in macro-environment burn-in chambers. Chamber specifications lay claim to airflow rates, and each chamber generally has a different specification. Thermal issues have exposed a weakness in these systems from maximizing the capabilities of advanced thermal control add-on components, and it is directly related to the variability of airflow rates at each individual site, as the heat site is inside the burn-in chamber. Figure 4 highlights the variability of airflow at various sites on boards as they site in two different slots within the chamber.
One option to eliminate this problem is to enhance the airflow of the system. The drawback in doing this effectively is at the expense of capacity within the chamber. Boards can be removed from specific slots to open spacing within the chamber, allowing for increased fluid airflow. Another option includes the introduction of alternative airflow enhancements that are staged at intermediate areas with the chamber’s cavity. In many cases, this also takes up space that is traditionally reserved for production capacity.
High-power, high-variance devices are driving the industry to see the burn-in process in a different light, allowing for the introduction of methods altering the paradigm that burn-in must be conducted in a macro-environment. Using a device and integrated thermal-solution heater, devices can be brought to burn-in temperatures. By using a heatsink and variable airflow source, thermal resistance of a heatsink can be increased or decreased for variation and control of device a device’s thermal dissipation.
The introduction of variable thermal-resistance solutions opens a new realm for burn-in operations where system constraints are removed from the equation. Semiconductor manufacturers can anticipate maximizing and using facility square footage through implementation of room temperature burn-in. Burn-in operations will use facility areas that encompass racks throughout the facility space that contain driver boards and burn-in boards in an open environment. By moving to a room temperature burn-in strategy, burn-in operations can begin to increase capacity, improve throughput and yield with thermal management integration, and begin to experience full entitlement of the facilities allotted for burn-in operations.
Change will continue to disrupt the semiconductor manufacturing process - particularly at the back end - and work to compromise existing efficiencies and margins. We already have experienced how the development of finer wafer-fabrication architecture and smaller node sizes on the front end has re-defined what we can consider effective thermal management and burn-in.
Chris Lopez, manager, thermal solutions, may be contacted at Antares Advanced Test Technologies, 2102 West Quail Ave., Ste 2, Phoenix, AZ 85027; 480-682-6147; E-mail: email@example.com.