Back-end Processes Take Center Stage at SEMICON West


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Whether the topic of discussion was yield management, reducing cost of production and test, the next area of industry expansion, or where a company is realizing the greatest revenue, back-end assembly and test was the focus at SEMICON West 2007.

“We’ve wrung as much as we can out of the front end,” noted Jeffrey Albelo, director of laser singulations group, Electro Scientific Industries, Inc., adding that ESI is 100% dedicated to back-end processes with its laser technologies. At the show, the company announced a UV tool for repairing DRAM failures at the wafer level that is said to increase yields to 90%.

“Advanced packaging is growing our business right now,” says Laura Rebouché, VP, investor relations, Ultratech. “It’s about 50% of our revenue.” The company, which formerly focused on front-end technologies, is one of the first to bring front-end technologies into the back-end with advanced packaging lithography tools, she added. 3D packaging will be significant for them.

In his opening keynote, Douglas Gross, senior VP for manufacturing and supply chain, AMD, talked about the company’s vision for efficiency. “The next evolution in semiconductor manufacturing is achieving ultimate efficiency in all our operations,” said Gross. “We have to transform the entire process of conceiving, producing, and delivering product.” He noted that back-end processes are as important as front-end operations. Back-end operations make up 50% of development costs. Part of the company’s roadmap is to “re-architect” back-end lines at their Singapore facility, reducing footprint and cycle times.

Wafer-level packaging, MEMS, and 3D stacked packages are driving developments in all areas of the process from wafer processing materials to dedicated tool sets and test devices. Rohm and Haas offers dielectrics targeted for packaging and through-silicon via (TSV) electroplating materials, noted Ken Gaglione, the company’s global marketing director. TSV is also a target market for EV Group, says Steve Dwyer, VP and general manager, EVG North America. EVG partnered with Brewer Science to create a temporary wafer bonding technology that combines Brewer’s wafer bond material with EVG’s bonding and debonding equipment platforms for processing sub-100-µm thinned wafers.

At NEXX Systems, whose electroplating and sputtering tools were developed specifically for back-end processes, there has been a shift from wafer bumping processes to TSVs and redistribution layer (RDL) processes for the Stratus electro-deposition plating tool, says Mark Welsh, manager, U.S. sales. No changes to the tool are necessary, he explained, it just lends itself to the application. The company has also been working with Cubic Wafer to develop 3D stacking processes.

FIGURE 1. In his keynote, Douglas Gross, senior VP for manufacturing and supply chain, AMD, discusses efficiency.
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Other front-end veterans are jumping on board the 3D train with vigor. SUSS MicroTec, whose lithography business increased 50% last year, with 30% in the packaging market, talked about their set of 3D integration tools for wafer bonding and lithography. The company’s philosophy, noted Michael Gustafson, VP sales, is to offer a full suite that can transfer the process upstream from research and production to full-volume manufacturing. SEZ Group, whose core competencies have been in the front-end with their single wet wafer processing, is also exploring opportunities in the packaging area for a dedicated tool set, says Heinz Oyrer, VP corporate planning, SEZ.

Jordan Valley has developed an X-ray-based metrology tool for measuring thin film thickness and composition. Measuring the RDL for under bump metallization (UBM) is one application of this tool, noted Isaac Mazor, CEO, who says Jordan Valley is the first to use small-spot, low-power X-ray to perform non-destructive analysis. The tool has also proven useful in measuring the composition of lead-free solder balls, which tend to have silver at the core. “Lead-free is providing a need to measure silver,” explained Mazor.

FormFactor introduced MEMS-based probe cards that enables sort, reliability, and final testing of devices at the wafer level, prior to dicing. “The cost-efficient way is to test on the wafer,” explained Igor Khandros, CEO, FormFactor.

For those of us who focus on advanced packaging processes and technologies on a daily basis, this year’s SEMICON West was an exciting and validating experience. Expect to see much more on new innovations that further enable Moore’s Law in the coming year.