Laser Applications in Advanced IC Packaging


Delivering a Bright Future


Much ado has been made over the need to wring increased performance out of the same silicon real estate and/or device structures. Technologists have been marching to this drumbeat ever since integration scaling was contemplated in the late 1960s. Device designers have adopted increasingly clever sets of materials and geometries, surpassing all expectations in delivering Moore of the same with each passing performance milestone. Specifically, the RC time delay was targeted for improvement somewhere between 180 and 110 nm, depending on the device, with the advent of large-scale copper interconnect and interlayer dielectrics of modified SiO2. Figure 1 illustrates this trend and provides a mathematical footing on which this phenomenon is based.

Faster switching was first accomplished by reducing the resistance component. Then capacitance was further modified by including so-called low-k materials. This, more accurately termed “lower-k,” material brought its own promise and problems, culminating in the ultra-low-k materials presently finding their way into limited production across architectures and applications. In the realm of electronic devices, physical layout is the last bastion of slowness to be defeated. Sending signals through circuits, instead of more direct pathways formed through the semiconducting substrates, results in delays.

Figure 1. Historical electrical delay in ICs as a function of node and first-order approximation of RC time delay in switching digital circuits.
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IBM recently announced production of devices using these layouts.1 Data travel distances have been reduced by a factor of 1000, while accommodating 100 times the I/O bandwidth of devices connected via traditional wire-bond technology. The desire to remove these barriers to faster e-computing has invigorated investigations into stacked or 3D package architectures. Ample developments in laser technology will likely yield the results necessary to drive commercialization efforts. Pilot production of a variety of memory and system-on-package (SoP) technologies has recently been seen in the marketplace.2

This 3D methodology uses, among other techniques, TSV to replace wire-bond structures. CSP also incorporates via drilling technology on a variety of levels for blind-via formation. These emergent and re-emergent techniques require via-drilling processes that are cost effective, robust, and ultimately scalable to support the rapid growth in the Z-dimension to maximize performance per mm2. This work focuses on these types of applications and their relationship to extant laser applications in CSP.

Figure 2. 50-µm vias in 300-µm Si drilled at a nominal run-rate of 200 vias per second.
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To develop baseline comparisons for determining suitability of a particular technology, various via sizes and aspect ratios were produced in single crystal and polycrystalline substrates. Laser drilling in all substrates was accomplished with DPSS or YAG lasers having average powers from 10 to 50 W of various wavelengths. 30-, 50-, 75-, 100-, 300-, and 400-µm Si 100 wafers were commercially obtained and used without further processing. Laser pulse repetition rates were all >10 KHz. Figure 2 shows the low-taper Si vias under consideration for TSV applications.

Table 1. Specifications for a competitive laser system.
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Using several novel laser techniques, trade-offs inherent in laser via-drilling solutions were investigated. Chief among them was the total number of vias drilled on a wafer. Frequently, this number is scaled for ease-of-comparison like “200-mm wafer equivalents” is used in compiling wafer-start data for 300-mm production. In this case, the scaled value is vias per 200-mm wafer. Initially, these values are computed from raw via-drill rates. Values per 1000 vias drilled are reported, since specific device layout issues begin to skew the results at higher via counts/200-mm wafer. Figure 3 provides an example via-drill rate for a 2-µm via in single crystal Si. By judicious choice of wavelength and power, these curves can be optimized for any particular application under consideration.3 Drill rates > 1200 vps have been realized for certain applications.

In addition to via-formation rate, investigations examined via quality and, specifically, the amount of damage to the material surrounding the via. Figure 4 shows the presence and absence of discernable heat-affected zone (HAZ) around the perimeter of vias drilled in punch mode. The volume of heat-affected material was modulated by pulse duration, substrate thickness, and via aspect ratio.

Figure 3. Via formation rates in Si vs. substrate thickness for a fixed via size of 25 µm.
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Statistics were collected from outside sources and through customer partnerships pursuant to deep reactive ion etch (DRIE) data for comparison purposes. Operational devices were prepared and are presently under evaluation for mechanical and electrical robustness, which is the first step in determining suitability for production. These structures comprise homogenous chips and stacked chip-to-chip (C2C), six layers tall. Interconnect between the layers is accomplished with TSV architecture.

Results and Discussion

Novel laser architectures and powers produce consequences that may result in smaller-pitch structures, cleaner vias, and ultimately a higher-yield process for the formation of stacked-chip TSV structures. A number of 3D IC markets can be envisioned, each with its attendant level of integration complexity and cost, on a via/200-mm wafer basis. This distribution represents where the market is now, and where it will be for the immediate future.

Figure 4. Via quality comparison as a function of laser pulsewidth. 50-µm vias in 770-µm Si. Damage to the Si may represent a potential failure mechanism or perhaps limit long-term device reliability.
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In terms of adoption of laser-based via formation, another way to divide the market for technology selection is to think in terms of drivers. For TSV memory applications, cost is the driving factor until the technology on which these memories are based changes. For all other TSV segments, performance is the driver, as the functionality and complexity of these devices is much higher than simple stacked DRAM or flash (Figure 5).

Figure 5. Distribution of TSV applications across primary market segments.
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Based on the raw via-drill-rate data, a normalized cost per 1000 vias has been obtained and can be compared against DRIE etching. The data in Figure 6 support the theory that laser costs are lower for all via counts below the flip chip boundary, which is a somewhat arbitrary demarcation after which flip chip I/O and packaging are applied due to the shear number of I/O required by the device. Since Samsung has already started down this pathway and the projected compound annual growth rate (CAGR) is 20-25% over the next five years, depending on assumptions, there exists an opportunity to develop idealized laser systems for addressing this market.

Figure 6. Normalized cost of laser-drilled TSV as a function of via count.
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Pending the results of long-short pulse duration split-lot experiments, there may be an opportunity to improve device yields using TSV over existing processes, while also increasing chip performance and available I/O count. This will lead to smaller and more complex devices occupying the same or smaller Si real estate, depending on integration. Based on these results, Table 1 lists specifications for a competitive laser system. Judicious choice of parameters will result in a cost-effective, high-yield process whereby large-scale integration of TSV can be realized.


While lasers have been used for various device packaging and interconnect applications, 4 the advent of CSP with TSV architectures represents an opportunity to bring laser processing into the forefront of advanced package applications. Also noteworthy is the opportunity to bring laser processing firmly into front-end-of-line (FEOL) production. This work, and recent announcements by Samsung and IBM, highlights the potential market that exists and also the existence of a path forward to realizing this technology in large-scale manufacturing.

Solutions to a number of key problems associated with integration are significant for continued growth and adoption of TSV. How are the vias to be filled? At what step in the production process are the vias to be formed? What kind of bonding technique is to be used and is the bonding scheme to be wafer-to-wafer (W2W) or C2C? These and other problems are being addressed in fab research organizations and laboratories all over the world.

TSV have been identified as a key technology in the continued quest for increased performance and miniaturization. Work is ongoing to examine the suitability of laser systems for drilling a wide variety of substrates important to advanced IC packaging efforts, including ceramics of variable stoichiometry, metal and rare earth oxides, and polymeric materials of layered composition.5 Indefatigably, the emergence of a mature and capable laser technology will ensure success of this approach and increase the envelope of applications to which TSV architectures are well suited.


I would like to acknowledge the excellent SEM work of Michael Nashner, Ph.D., and the technical assistance of Peter Pirogovsky, Ph.D., and Jim O’Brien, without whom this work would never see the light of day.


  1. IBM Press Release, April 13, 2007,
  2. Samsung Press Release, April 24, 2007,
  3. US Patent No. 7,157,038 B2, Baird, et al.
  4. “Laser-Drilled Blind Vias Increase PCB Real Estate,” Dana Korf, Electronic Packaging & Production, 1987, pp 56-57 and US Patent No. 4, 642, 160, Burgess.
  5. ESI internal communications re: High Average Power Ultrafast Lasers and TSV Production, January 2007.

JEFFREY ALBELO, director of laser singulation solutions group, may be contacted at Electro Schientific Industries, Inc., Portland, OR; 503/671-5624;