Handling Ultra-thin Wafers


Mobile Electrostatic Carriers Enable Bumping


Manufacturing technologies for 50- to 150-µm thin wafers are a basic need for a wide variety of microelectronic products. Further technological developments are targeting stacked-die assemblies, vertical system integration, and many new ideas for MEMS devices, which are based on wafer-bonding technologies. These require new handling techniques for processes that must be performed on the backside of thin or fragile substrates.

A practical solution for thin-wafer processing is a new carrier technique that uses electrostatic forces for reversible attachment of thin and fragile wafers to a rigid support substrate. This concept - a mobile electrostatic carrier1 - is based on carrier substrates that are fully compatible to standard wafer-handling equipment, and allows long duration times for electrostatic clamping even after the power supply is disconnected.

Figure 1. Principle of electrostatic attraction between a mobile electrostatic carrier and a thin device wafer.
Click here to enlarge image

Semiconductor materials like silicon or gallium arsenide (GaAs) wafers can be fixed onto a carrier substrate by electrostatic forces. The basic mechanism has been used for many years in electrostatic wafer chucks. However, these are an integral part of processing equipment and cannot be used for transport or handling of thin or fragile wafers.

To derive a mobile wafer support system, the electrostatic plate should be the size and shape of a standard wafer and must maintain electrostatic attraction, after disconnecting an external power supply, over a long period of time. Attractive electrical fields need to be frozen within dielectric cover layers, which allow storage of charge carriers or orientation of molecular dipoles. It has been proven that layers of permanent electrical polarization can be prepared on top of a silicon base wafer. Thereby, a mobile electrostatic carrier is realized that shows the same thermal properties as a thin silicon device wafer to be reversibly bonded onto a stabilizing support substrate.

Figure 1 shows a cross section of the wafer stack configuration. A thin or fragile semiconductor substrate is placed on top of the carrier and electrode areas are charged by a power supply. Attractive forces are evoked by the electrical fields between the backside of the thin device wafer and the electrode areas of the carrier substrate.

Preparation and Characterization

Figure 2 shows an example of a mobile electrostatic carrier prepared on a silicon wafer substrate and the adjacent hand-held charging unit, which provides 200-V DC voltage to initiate the electrostatic fixation. First, a thin wafer is placed onto the carrier. The charging unit is connected to the contact pads to initiate electrostatic clamping, and then disconnected from the power supply. Within a few seconds the stacked wafer pair is ready for further processing.

Figure 2. Mobile electrostatic carrier made on silicon wafer substrate and hand-held power supply.
Click here to enlarge image

A unique property of this carrier technology is the absence of any polymeric bonding material. Bonding and de-bonding of thin wafers onto electrostatic carriers can be achieved quickly, in a repeatable manner, and without any constraints regarding surface contaminants from bonding agents.

It was important to characterize the long-term stability of the carrier’s polarization state, and corresponding holding forces. To achieve these technical data, the voltage decay at the mobile electrostatic carriers’ contact pads was measured after removing the power supply and with a thin wafer attached to the carrier. Results (Figure 3) support the conclusion that the charging status of the carriers remains constant for many days at ambient temperature. This offers a new and simple technical solution for transport, storage, and handling of thin and fragile wafers. The long duration time of the carrier’s polarized state is also confirmed by fitting experimental data with an exponential decay curve. Fit results indicate a high portion of constant polarization at approximately 160 V, when initial charging was performed at 200 V. This electrical property is an additional physical effect and exceeds the known Coulomb-type behavior of a standard capacitor.

Figure 3. Electrostatic potential measured at a mobile electrostatic carrier after removal of charging unit, performed at 23°C.
Click here to enlarge image

The most important feature of this carrier technique is its ability to maintain electrostatic attraction even at elevated temperatures. It has already been shown that electrostatic holding forces remain active at temperatures above 400°C. No other reversible bonding technique offers processing capabilities in this temperature region.

Figure 4. Thinned wafer attached onto a mobile electrostatic carrier and placed in a standard quartz boat.
Click here to enlarge image

Several applications of mobile electrostatic carriers for thin wafer processing have already been tested and have proven the technical potential of this new carrier concept.Plasma processes at the backside of thin wafers are an interesting application example. They might be used during stress-relief plasma etching after backside grinding, via etching for 3D integration of stacked dies, and deposition of PECVD silicon oxide or nitride layers for electrical insulation and passivation. Further applications are targeting metal deposition at the backside of thin wafers and sintering of metal layers.

Thinned Wafer Bumping

Solder bumps are widely used for flip chip assemblies and chip-scale package (CSP) technologies. A common goal of thinner chip assemblies requires a steady reduction of the chip thickness itself. Wafer-thinning sequences are based on a mechanical grinding process performed at the backside of device wafers. However, risk of wafer breakage dramatically increases in the case of large surface topographies; for example, with solder balls whose diameter may be in the 50-150 µm range.

Until now, thinning of such wafers was limited to thickness values above 200 µm. A new approach would change the process sequence from thinning-after-bumping to thinning-before-bumping.2 This concept was successfully conducted with 55-µm-thick test wafers, and bears no restrictions with regard to solder ball topography, wafer thickness, or diameter.

The process flow for bumping of thinned wafers began with the deposition of nickel/gold under bump metallization (UBM) on top of test wafers. Next, the wafers were reversibly bonded onto a silicon substrate by means of double-side adhesive thermal release tape. Wafers were ground and wet-chemically etched to a final thickness of 50-80 µm. At this point, sequence-thinned wafers were still supported by tape and carrier wafer. The backsides of test wafers were attached on top of a mobile electrostatic carrier whose electrodes were charged to initiate the clamping. This triple-wafer stack was then placed onto a hotplate and heated to 100°C. Consequently, adhesion of thermal release tape dropped to zero and the first carrier was removed. Thinned wafers were securely transferred onto the electrostatic carrier within 2 minutes, and could enter bumping process steps: deposition of solder paste by screen printing and reflow of solder material at temperatures around 250°C. All equipment involved was used in its standard configuration.

Figure 5. 55-µm-thin test wafer fixed onto a mobile electrostatic carrier.
Click here to enlarge image

Figure 5 shows an example of a 55-µm-thin, 150-mm-diameter test wafer attached to a mobile electrostatic carrier. Solder balls are already formed and are visible along the chip layout. After bumping, wafers were removed from the carrier and diced by a conventional wafer saw. Final scanning electron microscopy (SEM) inspection shows the relation between chip thickness and solder ball dimensions (Figure 6).

Figure 6. 140-µm-diameter solder ball bumps on top of 55-µm-thin single chips; bumping was performed after thinning.
Click here to enlarge image

Development Status
Manufacture of electrostatic carriers on silicon wafer substrates by thin-film technology paved the way to a high-performance carrier technology. A wafer carrier technique could be realized that offers high thermal conductivity, and flat and uniform support substrates. Furthermore, with silicon as a base material, the support system is fully compatible with standard wafer fab requirements. The next important development step will be the realization of via holes through the wafer substrate to enable backside contact pads for charging and discharging of the electrode areas. Ongoing research work is also focusing on the basic physical principles responsible for the permanent polarization state of dielectric layers. This knowledge may enable further improved properties of mobile electrostatic carriers in terms of high temperature and long-term stability of the electrostatic bonding mechanism.


  1. 1. U.S. patent US 7,027,283 B2
  2. German patent application DE 10 2004 021 259 A1

Contact the authors for a complete list of references.

Christof Landesberger; Sabine Scherbaum; Dieter Bollman; and Karlheinz Bock, Ph. D., may be contacted at the Fraunhofer-Institute for Reliability and Microintegration IZM, Hansastr. 27d, 80686 Munich, Germany; +49 (0) 89 54759295; E-mail: