Innovative Method for Bonding and Interconnect: A 3D Subsystem Solution


By WILFRIED BAIR, Ziptronix, Inc.

Novel wafer-level 3D technologies will enable cell phone and other mobile equipment designers to achieve greater circuit density and/or significant cost savings, versus designs that make use of chips in traditional leadframe packages.

These highly integrated, fully tested, 3D subsystems can be constructed in a variety of ways. Most are focused on a multiple stacked-die package system interconnected by multi-level internal wire bonding or wafer bumping. Various package-in-package (PiP) and package-on-package (PoP) architectures are examples of this approach.

However, it may be difficult to produce a mixed-signal subsystem without compromises that impact either the circuit’s performance or the economic logic that initially led to the 3D approach.

Many stacking schemes require excluding active and passive devices from large areas of the die to reserve space for bonding pads or bumps. The lower density may affect system performance. Additionally, it is difficult to interconnect multiple die using wire-bonding or bumping techniques without also reducing system bandwidth.

But what if packages could be done away with entirely, and multiple bare die could be bonded and interconnected directly onto a board-mountable substrate?

Begin with the Bond

Most existing wafer-level bonding methods require a combination of adhesives, heat, and/or pressure, all of which can destroy active devices on a die and compromise placement accuracy.

There is one approach which integrates direct oxide bonding with high-density interconnect. A strong oxide bond and a hermetic seal is formed between bare die and a board-mountable substrate without the requisite adhesive, heat, or pressure. The substrate contains embedded, fine-pitch metal routing lines which match to I/O signal paths of each die, and eliminate long, slow, power-consuming delays.

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The bonding mechanism is not limited to silicon, so the dice mounted onto the substrate can be made from any semiconductor material, making it possible to integrate a cell phone’s digital logic, RF front-end, and analog functions into a fully tested, verified subsystem. The dice and silicon substrate can be thinned to about 30 µm regardless of the semiconductor material from which each die is made, and the substrate with the dice bonded to it can be board-mounted using conventional techniques.

Conceptually, the process starts with completed, known good die (KGD) that are flipped upside down and bonded at room temperature to the wafer. Covalent bond energy is the mechanism by which the direct bond and hermetic seal are created. No individual plastic or ceramic leadframe packages are required.

Using through-silicon vias (TSVs), metal lines run through to the other side of the substrate, where they terminate in whatever architecture is desired to mount the substrate - solder bumps, landing pads, etc. - eliminating the need to mount individually packaged die to FR4 PCBs.

Forming the Interconnects

Standard wafer-thinning exposes the respective connection points of a die’s interconnect and the metal lines embedded in the silicon substrate. This is followed by deposition of a thin layer of silicon oxide (SiO2) and fine-pitch metal posts. A chemical mechanical polishing (CMP) step is added to achieve a micro-roughness of approximately 0.5-nm RMS. Following CMP, a cleaning process is applied to both surfaces. This is followed by chemical surface activation, and then the two surfaces are aligned so the connection points will meet. More than 1,000,000 electrical connections per square centimeter can be achieved.

The oxide is activated using a proprietary method, and once the surfaces make contact, the bond is initiated within two to four seconds at room temperature. Its ultimate strength typically exceeds the fracture strength of the bonded bulk materials.


This wafer-level process is accomplished in a batch mode; thus, it is inherently lower-cost than other approaches and lends itself to producing low-profile, high-density parts that can be used in high-throughput electronics manufacturing operations. It also produces parts that are inherently more reliable, since traditional packaging-related failure points (solder joints, wire bonds, etc.) are eliminated.

Wilfried Bair, V.P marketing and business development, may be contacted at Ziptronix, Inc., 800 Perimeter Park, Suite B, Morrisville, NC 27560; 919/459-2444; E-mail: