Issue



Technology Investment Strategies to Meet Future Product Needs


03/01/2007







t the 2007 Consumer Electronics Show (CES), convergence, or the merging of PCs, TVs, cell phones, and other devices that enable access to diverse and growing content, was a key theme. The number and diversity of available products has increased significantly. Now every notebook must have wireless communications. Home entertainment devices come with a digital interface (HDMI), and computers are used for storing content and enjoying music and videos. Similarly, as convergence grows, computing becomes more personalized, creating new usage models such as personal media players and the digital-health tablet PC.

Challenges of processing, transmitting, and storing multi-media information across different types of devices are still large and daunting. Device manufacturers continue to take advantage of Moore’s Law to provide more computing capability and higher storage densities in each new generation of silicon. Silicon technology continues to become more complex with the integration of lower dielectric constant (Dk) materials and new transistor structures to improve performance-per-watt. Packaging must integrate new silicon and product features into smaller and lower-cost form factors. Legislation to remove potentially hazardous materials progressively makes our jobs more challenging. Delivering packaging technologies to support these trends presents an opportunity to refine key technology development investments and methods. Several strategies should be considered.

1. Invest in solutions to better isolate silicon from package, and package from system mechanical stresses. This would replace rigid lead-free bumps and package substrates with novel pliant interconnect structures and materials (think thin substrates). Ensuring that die or package stress is absorbed instead of transmitted would allow engineers to decouple packaging solutions from extreme application conditions (e.g. drop, vibration) and protect weaker silicon structures (e.g. inner layer dielectric). These novel solutions must be delivered without compromising electrical performance. Developing board-level underfill systems would improve manufacturing properties and eliminate barriers to reducing package size due to reliability and cost concerns. Novel catalyst technologies, alternative resins, and nanotechnology advancements can provide solutions.

2. Anticipate and pre-develop the likely winners. It’s unrealistic to think we can predict and cost-effectively develop every possible package technology variation. But one fundamental trend will likely remain true: smaller is better. Average selling prices for these devices will continue to decline or remain flat while more functionality is enabled. System-level trade-offs are necessary to achieve overall lower cost by allowing one new, and potentially higher cost, ingredient technology to enable cost savings elsewhere in the system. Invest in technologies that remove historical barriers to reducing package size, such as material-handling keep-out zones, BGA joint reliability, and PCB cost, as these will have a higher probability of adoption.

3. Invest in capabilities to improve development agility. To meet the demands of a rapidly changing marketplace, elements of packaging and assembly-/test-development methods must be re-examined so the speed at which technology is adapted can be improved. Traditional bottlenecks in the development process include characterization of key material and process steps, equipment development and tooling lead-time, product design validation, and reliability testing. Investing in capabilities to provide in-situ automated data collection for key equipment process parameters, and developing fully validated electrical design and analysis (EDA) tools for instant package model extractions would improve package characterization. Developing methods to simulate electrical, thermal, and structural integrity of packaging is critical. Driving strategies to create modular equipment architectures, such as re-configurable modular test, can reduce product and form-factor changes from protracted equipment development to relatively simple tooling changes. Lastly, industry standards must also adapt to new market realities. The processes that we use to establish, challenge, and revise our standards must be re-examined to ensure timely revisions to problematic issues such as package warpage, lead-free materials, and reliability testing conditions for emerging market segments.

The opportunity to provide innovative packaging technology solutions to meet new demands of converged computing and communications devices is upon us. Each of us has a role to play to ensure we understand the implications and proactively develop solutions for the next era.

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Nasser Grayeli, Ph.D., director of assembly & test technology development, VP, technology manufacturing group, may be contacted at Intel Corporation, 5000 W. Chandler Blvd, Chandler, AZ, 85226; 480/554-5375; E-mail: nasser.grayeli@intel.com.