Compact Thermal Modeling: Impacting the industry
BY SARANG SHIDORE, Flomerics, Inc.
imulation tools for thermal modeling of semiconductor packages have become routine in most design processes. Early spreadsheet tools have given way to sophisticated finite element analysis (FEA) or computational fluid dynamics (CFD) tools that interface mechanical CAD data directly into their analysis. Modeling is a necessary step, especially at early stages of thermal design, during which feasibility studies can narrow the spectrum of possible design choices. It is also used at later stages of the design for verification and design optimization.
A detailed thermal model (DTM) attempts to represent or reconstruct the physical geometry of a package to the extent that is feasible. Thus, the DTM will always look similar to the actual package geometry. Constructing a DTM in a thermal analysis tool is aided by the integration of part mechanical CAD data. A properly constructed detailed model is, by definition, boundary condition independent (BCI). For example, the model will accurately predict temperature at various points within the package - including junction, case, and leads - regardless of the cooling environment in which it is placed.
DTMs are suitable for use in design simulations consisting of few packages. For example, typical package thermal characterization problems - such as calculations to extract junction-to-ambient air thermal resistance (Θja) or junction-to-moving air thermal resistance (Θjma) - fall under this category. However, DTMs are not feasible for simulations of sub-systems or system-level computations involving numerous semiconductor packages because the computational resources required for solving large problems would be excessive if each represented a DTM package. These are the applications where a compact thermal model (CTM) should be used.
A CTM is a behavioral model that aims to predict package temperature accurately at only a few critical points - for example, junction, case, and leads - using far less computational effort. A CTM is not constructed by trying to mimic the geometry and material properties of the actual component. Rather, it is an abstraction of the component response to the environment in which it is placed. Most CTM approaches use a thermal resistor network to construct the model, in analogy with an electrical network that follows Ohm’s law. Two-resistor and a model developed by the Development of Libraries and Physical Models for an Integrated Design Environment (DELPHI) are two types of CTM in use today.
Two-resistor Compact Thermal Model
A simple, widely used CTM is a two-resistor model (Figure 1) consisting of a junction-to-board resistance (Θjb), and a junction-to-case resistance (Θjc). Both these parameters are defined by JEDEC as reference standards.1
Figure 1. A two-resistor compact thermal model.
Θjc is normally derived from a top cold plate test in which the package is placed on a board with all sides insulated except the top surface. A cold plate is pressed against the top surface at a specified temperature. Most of the power dissipated from the package leaves through its top (isothermal) surface. The one-dimensional equivalent of Fourier’s law is then applied to derive Θjc. Thus, Θjc = (Tj - Tcld)/P, where Tj is the junction temperature and Tcld is the temperature of the cold plate.
Θjb is derived by placing the package in a specially constructed harness called the ring cold plate (Figure 2). This fixture consists of a 4-layer PCB inserted between two cold plates in the shape of a ring. Thus, heat travels from the package through some distance within the board, and then out of the fixture through the coolant fluid in the cold plate.
Figure 2. Fixture for measuring Θjb.
Rjb is calculated by using the one-dimensional version of Fourier’s law: Θjb = (Tj - Tb)/P. The board temperature (Tb) is taken as the temperature at a point on the board surface located in the middle of the longest side of the package, no more than 1 mm from the package edge for an area array package, and on the center lead foot for a surface-mount leaded package.
A two-resistor model has a simple and intuitive structure. It can be created from existing test data and result in a significant increase in accuracy when predicting junction temperature as compared to traditional single-resistor metrics such as Θja.
DELPHI Compact Thermal Model
Coming up with a generalized methodology to generate a BCI CTM was a compact modeling challenge. To that end, the DELPHI consortium, made up of a number of primarily end-user companies, concluded a publicly funded research project that led to the first comprehensive methodology for the generation of BCI compact models.2 One of the key advantages of the DELPHI methodology is that it is non-proprietary and vendor/tool independent. The DELPHI method was followed up by the Supplier Evaluation and Exploitation of DELPHI (SEED) project, in which component suppliers evaluated the DELPHI model and found that it could be used satisfactorily as a predictive tool for junction temperature.3
Figure 3. A typical DELPHI compact model topology.
DELPHI compact models (Figure 3) are made up of several thermal resistors that connect a junction node (representing the die) to several surface nodes. Thermal links are also allowed between the surface nodes (shunt resistors).
The resistor network is derived from a step-by-step simulation and statistical optimization process that minimizes the error in junction temperature and heat flux over a wide spectrum of environments such as high-/low-conductivity PCB, bare package, package with heatsink, natural convection cooling, and fan cooling. The end result is a CTM that provides a predictive accuracy of junction temperature and major fluxes to within 10% - a major improvement over the accuracy of a two-resistor model.
The use of two-resistor and DELPHI CTMs is becoming wide-spread in the industry, just as the standardization process for these methodologies is at its final stages.
Emerging Standards for Thermal Modeling
Thermal design in the electronics industry is often an afterthought in the product cycle. Some organizations have been successful in bringing this task to an earlier stage. Still, in many cases, thermal engineers often have to work in a reactive rather than proactive mode.
This will no longer be the case in a well-integrated design chain wherein there is a seamless transfer of data and other information between semiconductor suppliers and system integrators. However, there are challenges that lie ahead before this can occur. Universal standards must be established, and a seamless data communication pathway between semiconductor suppliers and end-users must be created.
The possibility that thermal analysis environments in various stages of a design chain may experience interoperability problems means that data exchange is a huge issue. The creation of sensible and universal industry standards for thermal modeling of semiconductor packages forms the key challenge.
The need for standards is understood. The challenge is to evolve them in ways that gain universal acceptance among vendors. This means they must not give an implicit advantage to any one vendor. At the same time, technology contributions by vendors that help define standards must be taken into account.
JEDEC has been busy working on this challenge. The JC15.1 subcommittee has put thermal data exchange standards at the top of its priority list. The JC15.1 roadmap for 2006-07 includes three overview guidelines for thermal modeling of semiconductor packages: a modeling overview, a compact thermal modeling overview, and a terms and definitions document for thermal modeling. The overview documents are designed to lay out the framework of subsequent guidelines and standards for thermal modeling of semiconductor packages. They also familiarize a designer new to thermal modeling with the terminology and fundamental principles in the field.
A guideline for a two-resistor CTM lays out the theoretical framework of the two-resistor model, its definition and construction, and also provides a recipe for its use in practical design applications. A guideline for a DELPHI CTM lays out the theoretical framework of the DELPHI methodology and explains how it could be applied to generate BCI models of typical packages. The vendor-neutral CTM data standard facilitates seamless exchange of data between semiconductor manufacturers and system integrators (end-users).
Preparatory work has commenced on standards for dynamic CTMs, i.e., those used for time-dependent simulations. A guideline document for detailed thermal models is also being developed.
The maximum benefit of the CTM approach hinges on the willingness and ability for semiconductor manufacturers to provide ready-to-use libraries in an accessible format. The idea of on-line libraries is attractive, but is still not a reality due to the lack of comprehensive thermal standards and issues regarding data security and access. However, the emerging JEDEC standards and the increasing penetration of collaborative design practices among all industry tiers may change the situation.
- Rosten H., Parry J., Lasance C. J. M. et al, “Final Report to SEMI-THERM XIII on the European-Funded Project DELPHI - The Development of Libraries and Physical Models for an Integrated Design Environment,” Proc. of the Thirteenth IEEE SEMI-THERM Symposium, Austin, TX USA, January 28-30, 1997.
- Pape H., Noebauer G., “Generation and Verification of Boundary Condition Independent Compact Thermal Models for Active Components According to the DELPHI/SEED Methods,” Proc. of SEMITHERM XV, 1999, San Diego, CA, pp. 201-211.
SARANG SHIDORE, director of web business, may be contacted at Flomerics, Inc., 1106 Clayton Lane, Suite 525W, Austin, TX 78723; 512/420-9273, ext. 203; E-mail: email@example.com.