A Next-Generation Chip-Scale Packaging Solution
BY SEAN MORAN; VERN SOLBERG; AND CHRISTOPHER P. WADE, Ph.D, Tessera Technologies, Inc.
Many of today’s advanced packages use solder ball contact arrays to make package-to-board or package-to-package level 2 electrical connections. Solder ball contacts have served the industry well and will continue to be used for a variety of applications. However, the contact density is approaching practical limitations for ball grid array (BGA) interconnection at fine pitches using SMT assembly approaches. The micro-contact chip-scale package (CSP) has been developed to address these needs, targeting key technology drivers such as reduced package pitch for high-density area-array CSP products, increased capability for high-density package-on-package (PoP) stacking at finer pitches and higher I/O, high reliability for mobile electronic applications, and lower overall package height and volume for mobile and other high-functional-density electronics. The main feature of the micro-contact substrate is the Ni/Au-plated copper bump, which allows for SMT assembly of the CSP to the board (Figure 1).
Figure 1. Left: Cross-section of a micro-contact bump soldered to a PCB. Right: SEM of a micro-contact bump 0.4-mm pitch array using "contacts-through" technology.
Improved Routing Density
The increased routing flexibility of the micro-contact bump pad allows package designers to shrink the package size by going to a finer pitch, or reduce package cost by using more relaxed line-space design rules with the existing pitch. The diameter of the micro-contact bump and associated solder joint is much smaller than a typical solder ball joint. By using a reduced-diameter pad for the bump interconnection, additional routing on both the substrate and the PC board is possible, enabling further package miniaturization. The alternative - relaxed line width and spacing requirements when compared to a similar BGA pitch - results in reduced manufacturing costs and higher substrate yields. For example, a common fine-pitch BGA package that uses 0.5-mm pitch has a typical solder-ball contact-pad diameter of 300 µm. Using 40-µm line width and 40-µm space design rules, it is possible to route only two conductors between adjacent pads. By comparison, the micro-contact bump pad can be reduced to a diameter of only 200 µm. With the same 40/40 design rule, three conductors can be routed between adjacent micro-contact bump pads. Alternatively, it is possible to route two conductors between micro-contact bump pads using more relaxed design rules (e.g. 50/50) compared with solder ball contacts (Figure 2).
Figure 2. Left: Standard BGA CSP showing less routing and higher standoff height. Right: micro-contact CSP showing increased routing or finer interconnect pitch and low standoff height.
High-density, Low-profile 3-D Packaging
Mobile applications such as flash memory and processor-plus-memory are driving the trend towards 3-D packaging. A key advantage to the stacking approach is that the individual package layers can be fully tested prior to assembly. The micro-contact approach can be readily stacked in a variety of package configurations at finer pitches and higher I/O densities than BGA packages (Figure 3). The four-layer wire-bonded micro-contact memory stack occupies less than half the height and volume of the equivalent PoP using BGA. The 64-layer flip chip micro-contact stack has a total height of 16 mm (or 0.25 mm per layer). In this package, there are more than 188 solder joints per layer, so that, with 64 layers, there are more than 12,000 solder joints in the package. The micro-contact interconnection also results in a much lower profile standoff from the PCB. The typical standoff height between the micro-contact substrate and the PCB pad is 125-200 µm (Figure 1), compared with a typical FBGA standoff height of 350-450 µm, depending on solder ball size.
Figure 3. Left: Four-layer micro-contact wire-bonded memory stack adjacent to conventional four-layer micro-stacked package. Right: 64-die flip chip micro-contact package.
The demands of computing and mobile electronics are also driving reliability requirements for next-generation packaging. Thermal cycling and drop tests are two of the key stress conditions that next-generation packages must be able to meet. The recent introduction of lead-free materials adds additional challenges, especially in the area of solder-joint reliability. The stacked micro-contact memory package shown in Figure 3 is a four-stack, center-wire-bonded structure with overall dimensions of 10.7 × 13.2 mm, and a die size of 8.3 × 9.3 mm. The package pitch is 0.65 mm with a total of 60 micro-contact solder joints. Lead-free Sn/Ag/Cu (SAC) solder was used for package stacking as well as board mounting. A 30-package sample was subjected to thermal cycling tests per specification IPC-9701 condition TC3 (-40°/+125°C). The results in Figure 4A show no failures up to 1000 cycles, with wearout occurring above 1000 cycles. In another example, micro-contact full-area-array daisy-chain test packages using 0.4-mm pitch (23 × 23 array) and 0.8-mm pitch (11 × 11 array), both with overall packaged dimensions of 10 × 10 mm, were soldered to test boards using SAC 305 lead-free solder paste. The micro-contact bumps and the SMT solder-joint cross section of the 0.4-mm-pitch package are shown in Figure 1. Drop testing was conducted on a sample size of 15 board-mounted packages per specification JEDEC JESD22-B111 (1500 gn) for both the 0.4- and 0.8-mm pitches. For the 0.4-mm-pitch package, there were no observed failures after more than 100 drops. The 0.8-mm-pitch package experienced its first failure after 59 drops. The Weibull plot for the 0.8-mm-pitch drop test results is shown in Figure 4B. These results demonstrate a high level of reliability that will enable micro-contact technology to meet or exceed the requirements for next-generation lead-free packaging.
The micro-contact fabrication process begins with a tri-metal layer Cu/Ni/Cu composite. The base alloy is a rolled annealed (RA) copper foil that is fabricated in thicknesses ranging from 50 to 125 µm. An electrodeposited (ED) Cu foil is electroplated on one side with a thin (0.8 to 1.0 µm) nickel alloy. The Ni-plated side of thisCu foil is then vacuum-clad roll laminated to the RA Cu base. This layer of ED Cu is available in a range of commercial thicknesses starting around 9 µm. The thicker layer of RA copper will eventually provide the actual bump features, while the thin layer of copper on the opposite side of the nickel is for in-package circuit routing. The nickel layer serves as an etch stop during formation of the circuitry and micro-contact bumps.
There are two typical methods for creating the micro-contact substrate (Figure 5). The first method, referred to as “contacts-out,” uses the Cu/Ni/Cu tri-metallic material as a base. The thin copper side is initially coated with photoresist. The resist is then imaged and developed, and the circuit pattern is chemically etched into the thin copper. Following resist removal, only the copper conductors remain on the surface of the nickel alloy core layer. Before further chemical etching processes are performed, a dielectric film is bonded over the circuit conductor surface. Compatible dielectrics include polyimide and glass fiber or aramid-reinforced laminate materials such as BT and FR4. To expose circuit features needed for die attach and wire bonding, the dielectric film may be selectively removed using a laser ablation process.
Figure 5. Top: Cross-section of the “contacts-out” micro-contact substrate. Bottom: Cross-section of the “contacts-through” micro-contact substrate.
Micro-contact bumps are formed through a two-stage chemical etching (subtractive) process followed by stripping the residual exposed Ni. A photo-imaged resist is first used to define the bump locations. All areas not coated with resist are pre-etched using a relatively aggressive etch process followed by less-aggressive fine etching that completes the contact profiles. The contact profile that results from this process tapers from a base diameter of 180 µm to just 80 µm at the tip when using 125-µm-thick RA Cu. Because the RA copper’s material thickness is very uniform, the heights of all contacts on the finished substrate are near perfect.
A liquid, photo-imageable soldermask is applied over the micro-contact bumps and circuitry, and then lithographically patterned to expose the bumps and pad contacts. All non-soldermask-coated features are finally plated with a thin layer of nickel and gold to complete the substrate-fabrication process.
In the second method, referred to as “contacts-through,” the micro-contact bumps are formed first, using the same etching method. The dielectric layer (e.g., polyimide) is patterned separately using a drilling or etching process. The patterned dielectric is then aligned and laminated to the bump side of the trimetal layer. Next, a protective film is applied over the bumps while the thin copper side of the trimetal is patterned to form the circuit layer, followed by soldermask deposition and patterning on the circuit side. When the protective film is removed, the exposed micro-contact bump and Cu circuit features are plated with nickel and gold, completing the process.
The micro-contact CSP uses Ni/Au-coated Cu bumps attached to a Cu circuit layer and laminated to a dielectric substrate. The small-diameter micro-contact bumps enable high-density contacts for area-array CSP products, high-density PoP stacking at high I/O and fine pitches, lower overall package height and volume, and high reliability for mobile applications using lead-free materials. These features make micro-contact CSP an attractive solution for next-generation packages.
Thanks to Long Huynh, Dan Buckminster, Dave Baker, and Bel Haba.
SEAN MORAN, program manager; VERN SOLBERG, senior applications engineer; and CHRISTOPHER P. WADE, Ph.D., senior program manager, may be contacted at Tessera Technologies, Inc., 3099 Orchard Drive, San Jose, CA 95134; 408/894-0700; E-mail: email@example.com, firstname.lastname@example.org, email@example.com.