Issue



Collective Hybrid Bonding for 3D IC Stacks


11/01/2008







The 3D stacked IC (3D-IC) approach calls for a combination of standard single damascene techniques, extreme wafer thinning, and direct Cu-Cu thermo-compression bonding. Defined as hybrid bonding, when a tacky polymer step is incorporated, a cost-effective, die-to-wafer integration processes is enabled.

BY ANNE JOURDAIN, BART SWINNEN, AND ERIC BEYNE, IMEC; and STEFAN PARGRIEDER, EV Group

An important aspect of 3D integration schemes is the ability to enable hetero-integration–the vertical stacking of devices built in different technologies resulting in smaller and potentially cheaper systems with reduced power consumption and increased performance compared to a conventional system-on-chip (SOC) approach.1 One approach for IC stacking and integration is called 3D-stacked IC (3D-SIC) (Figure 1), in which standard single damascene techniques are combined with extreme wafer thinning and direct Cu-Cu thermo-compression bonding. 2,3

The original bonding process, consisting of pure Cu-to-Cu thermo-compression bonding, has been slightly modified by the inclusion of an additional patterned and compliant glue layer between stacked dice.4 This process is defined as hybrid bonding. The polymer layer mechanically stabilizes the extremely thin top die after bonding and carrier release, and also supports the stacked die in areas where there are little or no electrically functional interconnections between the dice. Hence, the inclusion of the dielectric glue layer enables stacking and electrical interconnection of dice with a highly non-uniform distribution of through-Si interconnects across the stack.

In principle, direct hybrid bonding is compatible with both die-to-die and wafer-to-wafer bonding. Wafer-to-wafer bonding has been the preferred method thus far, as it outperforms die-bonding in terms of alignment accuracy capabilities, which enables higher 3D interconnect densities. However, wafer-to-wafer 3D integration schemes inherently are limited to stacking dice of equal size. Moreover, when 2D device yield is limited, it leads to an important system yield loss. Therefore, wafer-to-wafer stacking will probably be cost effective only in specific markets.

Die-to-wafer stacking, on the other hand, may be of more interest for the fabrication of heterogeneously integrated systems as it does not impose the requirement of equal die size. The method is also compatible with the selection of known good die (KDG) prior to stacking and, therefore, is of interest in cases where one of the components in the stacked system is a product with limited yield. However, the cost of die-to-die or die-to-wafer stacking for most bonding methods is limited by the process throughput, especially when heat needs to be applied to achieve the bond, which is a lengthy process.


Figure 1. Illustration of the 3D-SIC concept showing a typical layout where 2 thin ICs (IC2 and IC3) are stacked upon a thicker device (IC1). Dice are separated by a thin dielectric glue layer and interconnected by TSVs.3
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The introduction of tacky polymer in the direct hybrid bonding scheme offers a possibility for die-to-wafer throughput optimization. The opportunity lies in the separation of pick-and-place and bonding operations. Figure 2 illustrates this concept, where the first TSV-dice are aligned and placed onto the landing wafer (Fig.2 left). The patterned and tacky dielectric that covers the landing wafer weakly bonds the stacked dice and fixes them during further handling. This operation can be performed at low temperatures, repeating the pick-and-place process until the full wafer is populated. In a second stage, the fully populated wafer is moved to a wafer-level bonding tool where pressure and heat are applied simultaneously to all stacked dice (Fig. 2 right). Thus, the dielectric reflows and the metallic interconnect bonding is performed for all stacked dice concurrently. This process is called collective hybrid bonding. While this process is still in its infancy, the method could be a first enabler for a cost-effective, die-to-wafer integration process with market entry points for memory stacking on top of logic or the stacking of logic dice.

Preparing the Landing Wafer

The sample preparation consists of post-processing a landing wafer with a thin-patterned and tacky polymer layer, and the pick-and-place of Cu nail dice on the landing wafer. The polymer layer is patterned by a standard photolithography step, and process parameters are adjusted so that the polymer layer thickness after patterning slightly exceeds the Cu-nail height. In this way, dice can be tentatively glued to the polymer without contacting the Cu nails of the top die to the Cu landing pads in the landing wafer (Figure 3). Post-bake or curing of the polymer is not realized at this point of the process flow.


Figure 2. Illustration of collective bonding process. (L) Die-to-wafer alignment and placement. (R) Collective bonding of all dice placed on the landing wafer.
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Pick-and-place of the Cu-nail dice is performed on a flip chip bonder at low temperature. The landing wafer is kept at room temperature for the whole duration of the procedure, allowing the polymer layer to remain sticky enough during die attach. After manual alignment of a Cu nail die to the landing wafer, the die is then attached to the glue layer on the landing wafer. While the time during which the contact force is maintained (touch-down time) varies depending on the glue layer used and on pick-and-place process parameters, touch-down times down to 1 sec/die have been demonstrated. In the case of an automatic alignment procedure, the indicative throughput that can potentially be achieved with currently known material is about 3600uph.

To demonstrate the process, ten dice have been placed on the same landing wafer as shown in Figure 5. In a production environment, a landing wafer can be fully populated with Cu-nail dice. It is very important to keep the touch-down temperature below the polymer reflow temperature to allow the polymer layer to flow and deform during collective bonding. The Cu-nails can land then and bond to the Cu landing pads to ensure they are electrically connected.

Collective Hybrid Bonding

After the fast pick-and-place operation, the landing wafer populated with 10 dice is transferred to a wafer bonder*, which is upgraded with a dedicated compliant top chuck made with a rubber pad for collective hybrid bonding applications. The goal of this compliant pad is to distribute the applied force during bonding uniformly across the different dies, even if they present a slight thickness difference.


Figure 3. Top die with 0.7µm Cu nails after recess etch.
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The collective bonding requires two steps. In the first, the temperature is increased to the polymer reflow temperature. The polymer layer starts to flow and, due to the applied pressure, begins to deform, contacting the Cu nails to the Cu landing pads. In the second step, the temperature is increased to the Cu bonding temperature (typically 300°C), allowing Cu-to-Cu bonding and the polymer curing to occur simultaneously. After bonding, all dies are successfully bonded to the landing wafer, without any visually detectable misalignment or damage after carrier release.


Figure 4. Landing wafer after collective bonding of 10 Cu nail dice (left) prior to release of the temporary carrier die (right) after temporary carrier release.
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A focused-ion-beam (FIB) cross section along a Cu nail shows a good mechanical contact between the Cu nail and the bottom metal pad, as well as good polymer bonding, confirming that the polymer flows and deforms upon the application of both force and temperature. A basic 2-point electrical measurement of 20 daisy chains showed electrical yield up to 1,000 TSVs as shown in Figure 5. The 50% electrical yield measured on the chains up to 10,000 TSVs is attributed to the particle inclusions, and is independent from the collective bonding process.


Figure 5. Electrical yield measured on 20 daisy chains up to 10k TSVs.
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Conclusion

Thanks to the inclusion of a thin polymer compliant layer between stacked dice, the possibility of separating the die-stacking operation in time from the die collective bonding process has been established. This creates an important opportunity for process cost reduction as cost is optimized by first populating a landing wafer with dice in a fast die-to-wafer stacking process, and second, collectively bonding all stacked dice in a wafer-level bonding process. Cross-section analysis and electrical measurements show very good mechanical and electrical contacts between the top and bottom metal layers, with a yield of 80% working daisy chains up to 1,000 TSVs.

References

  1. E. Beyne, “3D System Integration Technologies”, Symposium on VLSI Technology, April 26-28, 2006, Hsinchu, Taïwan.
  2. B. Swinnen, W. Ruythooren, P. De Moor, L. Bogaerts, L. Carbonell, K. De Munck, B. Eyckens, S. Stoukatch, D. Sabuncuoglu Tezcan, Z. Tokei, J. Vaes, J. Van Aelst and E. Beyne, “3D integration by Cu-Cu thermocompression bonding of extremely thinned bulk Si die containing 10µm pitch through Si vias”, Proc. IEDM Conference, December 11-13, 2006, San Francisco.
  3. A. Jourdain, S. Stoukatch, P. De Moor, W. Ruythooren, S. Pargfrieder, B. Swinnen and E. Beyne,, “Simultaneous Cu-Cu and Compliant Dielectric Bonding for 3D Stacking of ICs”, Proc. IITC Conference, June 4-6, 2007, Burlingame, CA, pp. 207-209.
  4. B. Swinnen, A. Jourdain, P. De Moor, E. Beyne C. in “Wafer Level 3-D ICs Process Technology”; edited by S. Tan, R.J. Gutmann, and L.R. Reif (Eds), Springer, ISBN 978-0-387-76532-7, 2008.


ANNE JOURDAIN, process integration engineer; BART SWINNEN, program manager; and ERIC BEYNE, scientific director, advanced packaging; may be contacted at IMEC VZW, Kapeldreef 75, B-3001 Leuven, Belgium; E-mail: jourdain@imec.be, swinnenb@imec.be, beyne@imec.be. STEFAN PARGFRIEDER, business development manager, may be contacted at EV Group, E. Thallner GmbH, DI Erich Thallner Strasse 1 A-4782 St.Florian/Inn, Austria; E-mail: S.Pargfrieder@EVGroup.com.