Issue



Reducing Costs for TSV Manufacturing


11/01/2008







Through silicon vias (TSVs) are a key component in 3D integration technology. TSV’s improve electrical performance, reduce power consumption, shrink device sizes, and potentially lower costs. CMOS image sensors are leading the way in TSV adoption, with microprocessors expected to follow.

BY KATHY COOK, SUSS MicroTec

Due to increasing interconnect densities and the rising cost of IC manufacturing in leading-edge technology nodes, 3D architectures for IC integration and packaging are becoming viable alternatives to traditional semiconductor manufacturing. 3D interconnect user applications include CMOS image sensors, memory, mixed signals, field programmable gate array (FPGA), and microprocessors. CMOS image sensors have led the way in the adoption of 3D interconnect using TSVs because of the enhancement in image quality and the reduction in device form factor that is possible using this technology (Figure 1).

Wafer bonding improves image quality by enabling sensors to be illuminated from the backside of the device. In traditional image sensor manufacturing, the metallization layers cover the sensors reducing the total light that hits the sensors. TSV technology eliminates the need for the metal layers to cover the sensors, thus allowing more light to be collected (Figure 2).


Figure 1. A camera module made using traditional semiconductor and packaging technology (left), vs. one made using 3D interconnect technology (right). Image courtesy of Tessera
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Performance will drive the utilization of TSV technology for advanced microprocessors. For other future applications, the potential for lowering the manufacturing costs will be an incentive to move toward 3D integration. Applications such as systems-on-a-chip (SOC) are based on the fabrication of a monolithic substrate integrating multiple devices. The cost of the entire SOC is determined by the most expensive device in the mix. 3D integration will reduce the overall cost of the SOC because each device process can be optimized according to the device type and its best known native process.

TSV Cost Structure Breakdown

As seen in Figure 3, Yole Développement lists wafer bonding as over 40% of the cost of TSV structures. The primary reason for this is the extremely low throughput involved in wafer bonding. The throughput is low because not only does wafer bonding require single wafer pair processing, but most bond processes must be done in a vacuum chamber. Ramping to the proper vacuum levels and processing temperatures takes time and must be repeated for each pair of wafers bonded. In addition, depending on the type of bond and the materials involved, the actual bond itself can take up to an hour, and in some cases, even longer. Because wafer bonding is responsible for such a high percentage of the cost of the TSV structures, it makes sense to focus cost reduction efforts on this part of the TSV manufacturing process.


TABLE 1. Overview of common bond types.
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Some of the methods for reducing the cost of the wafer bonding portion of TSV manufacturing include optimizing the bond type and material selection to reduce the actual bond time, increasing bonding equipment throughput through faster temperature and pressure ramp rates, and choosing the appropriate automated bonding equipment to achieve the lowest overall cost of ownership.

Optimizing Bond Type and Material

There are numerous combinations of bond materials and types that are suitable for 3D integration. Table 1 shows an overview of some commonly used bond types and the advantages and disadvantages of each one.

Metal bonding offers the unique advantage of allowing the electrical and mechanical connection to be made simultaneously. However, the metals themselves can be expensive and must have a minimal amount of oxidation to make a strong bond. In addition, these bonds must be completed at elevated temperatures and pressures, and the bond itself takes much longer than a direct bond, resulting in comparatively reduced throughput.

Adhesive bonding is more tolerant of substrate surface roughness, but its bond quality is less desirable than the other two types of bonding. In addition, post-bond alignment accuracy is typically not as good.

Direct bonding can be done at room temperature and pressure and does not require an intermediate layer of material. Therefore, throughput can be drastically improved. However, this method is extremely sensitive to particles and requires an extremely low micro-roughness on the substrate surface. There is often an additional chemical mechanical polishing (CMP) step involved in manufacturing to achieve the micro-roughness levels required for strong direct bonds. This reduces the overall throughput of the process and adds significantly to the cost of manufacturing.

Increasing Equipment Throughput

Automated bonding can be divided into three main steps:

  • Wafer handling
  • Wafer-to-wafer alignment
  • Wafer bonding

Of these three steps for metal and adhesive types of bonds, the bond step is the bottleneck of the entire process. Most of the opportunity to increase equipment throughput comes from improvements made within the bond chamber itself.

Most bonds are done at elevated temperatures and pressures, so the ramp rate of these two variables has a direct effect on the throughput of the equipment once the wafer has entered the chamber. The capability of loading and unloading the wafers from the chamber at elevated temperatures also increases the throughput. An automated wafer bonder capable of a heating rate of 30°C/min.and a cooling rate of 20°C/min. has been developed. In addition, this new bonder can be loaded and unloaded at a temperature of 350°C; 50°C higher than the previous platform.

Application-specific Process Modules

Each application dictates the specific requirements for bond equipment needed to achieve strong, void-free bonds at the lowest possible cost of ownership. For example, bonding a handle wafer to a CMOS image sensor wafer prior to back-thinning doesn’t require nearly as high a force or temperature as bonding the CMOS image sensor wafer to a logic wafer using copper as the interconnect material. A low-temperature, low-force bond chamber is less expensive than its high-force, high-temperature counterpart. A 300mm automated bond cluster* is available that can be configured with the exact process modules necessary for the application for which it is intended. In addition, the process modules can be changed as the process or manufacturing requirements dictate.


Figure 3. TSV cost structure breakdown. Source: Yole Développment
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Conclusion

Wafer bonding is an enabling technology for 3D integration, and it is responsible for a large portion of the cost of TSV structures. To reduce the cost per structure, there are several factors that should be addressed. The first is the type of bond to be used and the material to be used as the bond interface. There are advantages and disadvantages of each bond type and material, including additional manufacturing steps, so each one should be considered carefully. Throughput is another issue since wafer bonding is slow compared to other manufacturing processes. Several recent advancements have been made that help to increase throughput in wafer bonders. Finally, having a good understanding of the specific application that the equipment will be used for is important so that the equipment with the lowest cost of ownership is selected.

* XBC300 from SUSS MicroTec


KATHY COOK, 3D business development, may be contacted at SUSS MicroTec, Inc. 228 Suss Dr., Waterbury Center, VT 05677; 800/685-7877; E-mail: Kathy.cook@suss.com.

References

Contact the author for a complete list of references