Improved Flip Chip Probing
Clean the wafer not the probe card
BY TERENCE COLLIER, CvInc.
Testing flip chip wafers can be challenging. The test structure has to take the special geometry of round bumps into consideration when compared to a flat bond pad of a traditional wafer. Hitting the bump with too much force can lead to both mechanical and electrical reliability issues. Additionally, the test structure must consider the protective oxide layer coating the bump, along with contamination from organic materials from the fabrication process that can lead to high contact resistance (CRES). A successful test solution incorporates elimination of CRES while successfully validating known good die (KGD). Traditionally, the probe card is cleaned after a specified number of tests. A better approach is to clean the wafer (reducing CRES and eliminating organic residue) followed by electrical test validation.
Figure 1. Traditional probe on flat pad
Chip scale probing (CSP) requires different techniques than traditional pads to probe the material. The electrical contacts for the wafers are miniature solder bumps that sit above the wafer plane. As a result, the geometry of the probe card and hardware are different.
Figures 1 and 2 demonstrate the difference between the two structures. Figure 1 depicts a traditional wafer pad using cantilever probe technology. The pads are flat surfaces that are contacted in a horizontal plane. Figure 2 demonstrates the probing required by the CSP. The bump sits above the plane of the wafer. The probe needle in this case makes contact by moving up and down in the z-axis. Wafer cleanliness, hardware settings, test hardware (probe card), contact resistance (CRES) and bump alloy material all greatly influence KGD. The best way to improve yield is by cleaning oxide and organic residue from the wafer bumps.
Process and Cleaning
Fabrication of flip chip wafers follow similar stages of wafer fabrication, except the layers are a few orders of magnitude thicker (for example, photo resist [PR] layers during wafer fab might only be tenths of a micron, whereas bump resist layers can be up to 80µm thick). Given these thick layers, it’s inevitable that there will be some resist residues remaining. Add solder reflow, and the bumps now have residual organics as well as unwanted oxide layers.
A typical electroplate flip chip assembly process is as follows:
- Clean the aluminum bond pad
- Apply seed metals of Ti and Cu/Al
- Define bump location with PR
- Plate the bump
- Remove photoresist
- Flux and reflow the bump
To make good electrical contact, the probe must break through the CRES layer described in Figure 3. Typically, this is accomplished by adding additional travel in the z-axis (referred to as overtravel). The additional travel crushes the bump, exposing fresh metal to contact the probe needle. If the CRES layer is not displaced enough, false failures occur because the resistance between the probe and bump can exceed test requirements for minimum resistance. If the overtravel is too high, then damage to both bump and the component below can occur. (Many devices now have active circuitry under the pads and excess force from the probe needle can damage this circuitry.) In time, both the oxide and residues will deposit onto the probe needle, which calls for cleaning the probe needle to avoid false failures.
The traditional approach to bring the probe needle back to zero resistance is to clean (scrub) the needle on an inline abrasive material. Another approach is to purchase more complex probe card geometry that does not become contaminated with oxides and organic residues as quickly. The cost of these cards can be significantly higher, but the throughput, cycle time, and improved yield are worth the cost.
Figure 2. Flip chip “vertical” probe
A better approach to cleaning probe cards is to clean the wafer/bumps prior to test. Cleaning bumps helps at test, and during subsequent down-stream operations as well. It has been found that in many cases, cleaning the bumps can extend probe card life by more than 5 to 10x. Cleaning the wafer eliminates the need for expensive probes and the damage that can occur when additional overtravel is added to break through contamination layers.
Figure 3. Typical flip chip fabrication process.
Yield loss is due to flux residue contamination of the probe needle. The flux forms a barrier between the needle and bump, preventing electrical contact. Yield losses of up to 20% or more can result if the issue is not addressed. Likewise, cleaning the probe needles reduces probe card life and increases test time. The residue can also impact performance of high-frequency devices.
As a result, it will be imperative for the process owner to understand the root cause of flux-poor cleanup and establish procedures to ensure removal. Though additional consumables may be required, associated yield gains, hardware life, and cycle-time gains more than compensate for the cost of raw materials.
CRES is the measured impedance between the probe tip (or socket) and the electrical output of the DUT. The typical impedance range of the metallics used for probes, sockets, pads, and bumps have values in the mΩ range. With continuous probing or insertions, contaminants build up causing the impedance to rise beyond time-zero values. This rise in impedance results in poor contact, electrical fails (opens, speed related fails, threshold voltage, and output current, etc), and reduced life of probe hardware.
The test hardware must be cleaned each time the CRES reaches a critical value. Otherwise, increased test time, process bottlenecks, and assembly issues become drains on resources and profit. Unfortunately the cleaning reduces the life of the probe hardware.
CRES can occur from various sources in the process. A common source of increased CRES is the residue remaining after bump fabrication. Other areas in the fabrication process also contribute to contamination, but flux residues can be a critical source in the early stages of process development.
Figure 4. The pink area shows the oxide on the bump.
Figures 4 and 5 demonstrate the benefits of cleaning the bumps. In figure 4 the bumps are shown to have an oxide level that can be typical of a wafer after reflow and storage. Oxide levels are quite high and would demonstrate high CRES during probing or require the process engineer to reflow to minimize oxide levels. Figure 5 demonstrates that the oxide level can indeed be reduced by over 70% of the original value. This first stab at the process can also be optimized by the process engineer to remove even more oxide, but in general the oxide thickness demonstrated here will improve test performance in addition to assembly processing.
Figure 5. Bumps that have been cleaned show reduced oxide levels (area under pink curve).
Earlier, we discussed that overtravel is required to punch through the oxide and residue level to make low resistance contact. Prior to cleaning, the oxide is measured to be 80Å deep at the critical point of 10 atomic percent (10% is a good number for both probing and assembly to provide stable process control and good yield). After cleaning, the 10% level is detected at 30 Å. Of note in both charts is the presence of organics. FTIR shows both flux and PR residues that were later removed effectively with BPS 125.
There are a number of traditional vertical and MEMS-type probe cards on the market. Basic designs are targeted at overcoming CRES while increasing the number of probes between cleans and minimizing bump damage. An entire industry is geared on the novel self-cleaning cards. While cards do help if the wafer is dirty, they require cleaning eventually. The problem is that probe geometries make it difficult to clean the contactor points without damaging needle tips.
Figure 6. Dirty probe card needles showing oxide and organic residues.
Removing the oxide has demonstrated that the most basic vertical card is the best solution. First one must remove the organic residues. In the past this had been accomplished by use of dry plasma. The dilemma becomes apparent in the discussion. Use O2 plasma to remove organic residues and the oxide grows; use Ar to remove oxide and it does little to remove the organics - rather they are sputtered elsewhere on the wafer and redeposited. A better approach is to use something similar to BPS125 to remove the organics and BPS172 to remove the oxide. Since these are wet processes, the entire bumps are cleaned rather than line-of-site as with most plasmas. Data presented at SEMICON WEST ’08 demonstrated the BPS solutions to be much more effective, since plasma cleaning left over 45% of the residues on the surface, while BPS was effective at stripping the surface entirely as well as minimizing oxide regrowth.
Figure 6 is an image of bumps after probing on dirty pads. Not only is probing impacted, but the particles picked up can later be redeposited on the wafer and lead to shorts and opens during assembly operations. Cleaning the wafer bumps greatly reduces this problem.
The traditional process for flip chip test has been to clean the probe card or purchase a card that cost 5 to 10x more than required for the job. By taking the strategy of cleaning the wafers, operational costs can be reduced. Throughput can be improved. And KGD can be increased without the use of ineffective plasma tools.
Terence Q. Collier, contributing editor, may be contacted at CVInc. 850 S. Greenville, Suite 108, Richardson, TX, 75081; 214/557-1568; E-mail: email@example.com.