EMC3D Consortium Achieves Cost Goal for TSV
SANTA CLARA, CA — Two years ago, the EMC3D Consortium, an open consortia of equipment and materials manufacturers, established itself and set out to develop a process flow and cost model for 3D integration. Focusing on via-first TSVs as the method of interconnect, the intention was to find a solution to achieving this for $200/wafer cost of ownership (CoO) on a 3-year timeline. It appears, however, that they’ve beaten their own goal ahead of schedule, according to the Sept. 4th announcement that a proprietary process flow, iTSV, is achievable at $189/wafer for a 10,000 wafers/month capacity line.
The key, according to Rozalia Beica, program manager of EMC3D and TSV director for Semitool, is via-first chip stacking technology using 5 ??30μm via feature sizes. She explained that these dimensions were selected because of the etch and deposition challenges they present, and the interest and customer requests. In fact, Beica added, customers have requested even more aggressive features with up to 10:1 aspect ratios. “We have decided to look into these types of features in more detail and develop processes that can overcome these limitations and be, in a cost effective way, successfully integrated,” she said.
Besides the ability to manufacturing higher density interconnects, another advantage of having smaller vias is the significant decrease in processing times for metallization step. Reduce processing times will result in increased throughput, thus lowering the processing costs associated with metallization.
“The cost model clearly shows that reducing via size will enable lower CoO,” explained Markus Wimplinger, technology development and IP director at consortium member EV Group. He added, however, that reduced dimensions require thinner wafers that require unique handling solutions. According to Beica, glass and silicon are being considered as part of a handling solution. In a market research published by Yole Développment, out of the 35 companies interviewed, more than 60% responded that they will be using wafer handling carrier, such as glass and silicon.
The integrated via-first process, done in the foundry at the back-end-of-line (BEOL), includes litho and hard mask for the etch process, DRIE for via creation, thermal and CVD liner and barrier, wet copper seed, copper electroplate fill, CMP and associated wafer cleans to complete the via. The wafers are then processed using standard CMOS technology and finally passed back to the TSV group for backside processing, including thinning, lithography, copper redistribution, solder bump, dicing, and die-to-wafer-placement using temporary adhesive bonding before the final die-attach step for a complete process flow. Beica explained that although wafer-to-wafer (W2W) stacking is considered a more favorable approach due to throughput, the cost of lost-good-die is estimated to be higher than the stacking costs associated with D2W stacking. Adding alignment of the chips and bonding will become more complex and difficult through W2W approach once disparate technologies start to be integrated in heterogeneous packaging and dies of different sizes will have to be stacked, she added.
According to Mark Scannell, micoelectronics program manager, CEA-Leti, the technology was developed to leverage existing infrastructure used in advanced CMOS and wafer-level packaging industries. The challenges, he explained lie with the integrated relationship of process steps, and with improving speed and accuracy of die-to-wafer placement during die attach. “Many of the unit processes are well understood and characterized,” he said, “The challenges now are to bring the technology to mass production in a cost-effective package.”
5x25μm TSV structures filled with ECD copper. (Courtesy of Semitool, a founding member of EMC3D)
Having crossed the first milestone, the consortium is ready to take it to the next level. “This model allows us to identify the cost improvement programs needed to bring the price below $145/wafer.” says Wimplinger.
According to Yoon-Chul Sohn, of Samsung SAIT, the next step is “to design an effective 3D structure for better electrical and thermal performance, and determine its relationship with material defects, mechanical stress, and electromigration of these features.”
Beica says these steps and reliability issues need to be thoroughly investigated before the process is fully transferred to production. Because EMC3D is an open consortium consisting of equipment manufactures and material companies that work together with research groups to address the issues of cost-effective manufacturing and integration, they do not have a unique process that is marketed or licensed. Unit processes are available to anyone interested and marketed by each member individually, noted Beica. “We work very closely together within consortium, using our own test designs for solving integration issues, and in supporting demos and requests of our customers,” she explained. “We’ve come a long way since the consortium started in 2006. We currently are in much better understanding of the processes we use, successfully apply and integrate them, and more accurately estimate the costs associated with TSV technology.”
-Françoise von Trapp
News in Brief
Surface Technology Systems (STS) and Sumitomo Precision Products Co., Ltd (SPP), announced the formation of SPP Global Business Services (SGBS). SGBS will be responsible for all sales, customer support and marketing activities for both SPP and STS globally.
STMicroelectronics, STATS ChipPAC, and Infineon Technologies AG have signed an agreement to jointly develop the next-generation of embedded wafer-level ball grid array (eWLB) technology, based on Infineon’s first-generation technology, for use in manufacturing future-generation semiconductor packages. A follow-on agreement calls for STATS ChipPAC Ltd. to provide manufacturing services for products based eWLB technology.
Advantest Corporation, manufacturer of semiconductor test equipment, has completed its buyout of Credence Systems GmbH (CSG), a manufacturer of test systems for automotive semiconductors. The newly formed company will operate under the name Advantest Europe Systems GmbH and be located in Amerang, Germany.
SUSS MicroTec Inc., Bonder Division headquarters and North American sales and service site for all SUSS products, has achieved ISO 9001 certification for having established a high level process and system-oriented quality management (QM) based on ISO 9001 standards. SUSS MicroTec Lithography GmbH, another division of the company, was certified in 2007.
After a two-year stint in Stuttgart, SEMICON Europa will be on the move once again, this time to Dresden, reportedly the largest semiconductor center in Europe; so-called Silicon Saxony. SEMICON Europa will welcome its members at the Messe Dresden from October 6-8, 2009.
TI Pushes for IEEE Standard Ratification
HOUSTON — As chips add functionality, and system designs evolve away from boards and toward multi-chip system-on-chip (SoC) architectures, developers of handheld and consumer electronics are faced with stricter pin and package constraints. Texas Instruments, Inc., a key member of the IEEE working group, is driving the ratification of the IEEE 1149.7 standard, a two-pin test and debug interface standard that supports half the number of pins of the IEEE 1149.1 technology, allowing developers to easily test and debug products with complex digital circuitry, multiple CPUs, and applications software in mobile and handheld communication devices. TI is also working with Freescale Semiconductor, Intel Corporation, Lauterbach Datentechnik GmbH, IPExtreme, ASSET InterTech, Inc., Corelis and GlobeTech Solutions to refine and identify implementation challenges, ensuring a streamlined and robust solution is ready for industry wide adoption.
Tegal to Acquire Alcatel Micro Machining Systems Product Line
PETALUMA, CA — Tegal Corporation announced an agreement with Alcatel Micro Machining Systems (AMMS) and Alcatel-Lucent to acquire their deep reactive ion etch (DRIE) and plasma-enhanced chemical vapor deposition (PECVD) products, and the related intellectual property (IP). The addition of these capabilities to Tegal’s plasma-etch and deposition systems will reportedly enable Tegal to further expand into MEMS and 3D wafer-level packaging (WLP) applications. The agreement includes acquisition of product assets, patents and IP and agreements with key suppliers and distributors. Gilbert Bellini, president, AMMS, will join Tegal’s Board of Directors, and a 6-person team of high-level employees from AMMS will support Tegal for the first six months.
According to Thomas Mika, Tegal president and CEO, Tegal has been asked by customers to produce DRIE tools and had been looking for an opportunity to expand into this technology through acquisition. Mika considers the agreement with AMMS a “logical centerpiece of the strategic plan that we’ve been formulating for the last few years.” He is excited about moving into “well-developed, existing and growing” markets in the MEMS industry as well as emerging markets in the future. Key drivers are automotive and mobile communications applications, with component integration that includes both passives and power devices. The addition of DRIE will also naturally enable Tegal to produce products with through silicon vias (TSVs), including image sensors and memory devices.
AMMS will continue to support their existing customer base. Tegal plans to offer both existing AMMS products and further develop the DRIE technology. They will work to integrate DRIE process modules into Tegal’s new multi-chamber bridge tool, with options for 200mm and 300mm chambers. In addition, Tegal will assume responsibility for AMMS’ joint development programs with key customers, as well as research and academic institutions. AMMS owns a license for the Bosch DRIE process that will not directly transfer to Tegal, but Tegal will work with Bosch directly.
Mika admits that AMMS has been challenged on gross margins, and that plans to move manufacturing, assembly, and final test operations to Tegal’s facilities in Petaluma should improve margins. Tegal expects to complete the move this calendar year. AMMS’ production facilities are in Annecy, France, and they have historically done a lot of outsourcing. Tegal’s model includes outsourcing a few critical components but keeping as much manufacturing as possible in-house.
-Julia Goldstein, Ph.D.
Dow Corning Compound Eyes Intel’s Multi-chip Packages
SAN FRANCISCO — Dow Corning unveiled a thermally conductive compound, called “TC-5688,” at the Intel Developer Forum, August 19-21 2008, touting it for use with Intel’s newest mobile microprocessor, the Intel Core2 Extreme mobile processor QX9300.
Power cycling data on a multi-chip tester. (Source: Dow Corning)
The significance of this non-curing thermal interface material (TIM) is its resistance to pump out, which has been seen with materials in the past. This makes it suitable for multi-chip packaging applications (Figure 1). The company says the material exhibits “extremely low thermal resistance” at 0.05??C-cm2/W and high thermal conductivity at 5.67 W/mK.
Andrew Lovell, industry marketing specialist at Dow Corning, explained that during power cycling, microprocessor die can flex due to coefficient of thermal expansion (CTE) mismatch, placing thermo-mechanical stress on a TIM. “Multi-chip packages may enhance these stresses due to potential die height offset and other factors,” he said. Dow Corning benchmarked its TC-5688 against two competing materials on a multi-chip tester that simulates a mobile processor. The device was power-cycled on for six minutes and then off for six minutes; the junction temperature reached ~85??C. The cycle was repeated ~2000 times.
“While the thermal grease and phase change material exhibit rapid and significant degradation of their thermal properties, TC-5688 shows almost no sign of change in performance,” said Lovell. The phase-change material that was tested showed breakdown after ~500 cycles.
In the Aug/Sept 2008 article, SEMICON Europa’s Advanced Packaging Conference Shifts Focus from TSV to WLP, Eef Bagernan’s name was mis-spelled. We apologize for this error. - AP Editors