Issue



fcPiP: The Marriage of Flip Chip and Wire Bond


10/01/2008







BY RAJ PENDSE, PhD. STATS ChipPAC, Inc.

Cellular handsets and mobile handheld products are defining a new application space that goes beyond the realm of traditional flip chip and 3D packaging. The demand for high performance and high I/O density on one hand, and the need for extreme miniaturization on the other, has led to new and unlikely packaging configurations that combine flip chip and wire bond interconnection, build-up and laminate substrate technology and package-level integration of disparate device functions through 3D die and package stacking. The optimum solution often lies in a judicious combination, or hybridization, of these seemingly dissimilar technologies and approaches.

Package-in-package (PiP) technology is one such innovative packaging solution. Traditional die stacking technologies have made impressive strides in the areas of memory stacking and logic/memory integration. However, this approach falls short when a main memory or high-speed cache memory has to be integrated with a logic ASIC or DSP function, since only limited test coverage of the memory device is achievable during wafer sort. This roadblock is resolved by the use of PiP technology, wherein the memory device can be procured as a fully tested and burned-in known-good component, and interconnected with other devices in bare-die form using conventional stacking techniques.

The PiP approach was first deployed in high-end cell phones to integrate a baseband chip and analog chip with high speed memory in the form of a pre-tested land grid array (LGA) package; each device being interconnected to a common substrate using wire bonds. A more customized variant of this architecture was later used to form the engine of a portable gaming device wherein a DRAM chip was bonded to the ASIC device by flip chip interconnection to function as a local memory. More recently, the baseband device uses flip chip interconnection to the substrate to meet the demands of high I/O density and high performance for the base band chip, while the memory component and an analog device are integrated with the baseband chip using wire bond interconnection (Figure 1a). Other innovative variations of PiP include a side-by-side flip chip die with the memory LGA spanning the top, and a QFN as the embedded package instead of an LGA.


Figure 1. a) fcPiP and b) fcFiPoP
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The development of the flip chip PiP (fcPiP) has helped spawn the genesis of unique capabilities to augment the packaging engineers’ system-in-package (SiP) technology tool box. Some of the building block technologies fostered by PiP packaging include bumped wafer thinning to levels approaching or lesser than the bump height itself while maintaining bump integrity; a cost effective substrate manufacturing process that provides a selective wire bondable (thick electroplated Ni-Au ) finish, while maintaining a Au-free metallurgy for the flip chip landing pads on the same side of the substrate; a compatible material set and process for combining underfill and molding within the same package; an underfill process and die/substrate layout methodology that enables a fine underfill “fillet” with sufficient room for wire bonding within a constrained space; and last but not least, innovative flip chip substrate design and interconnection schemes such as bump-on-lead (BOL), that enable dense escape routing of die I/O without stretching substrate design rules.

Another approach for combining memory and baseband functions is package-on-package (PoP). PoP offers flexibility for the end customer to insert memory into the system at the final point of assembly versus committing it early at the component level. A new PiP solution called fan-in PoP (FiPoP) has been developed to marry the benefits of the PoP and PiP architectures. (Figure 1b). FiPoP incorporates a wire bonded interposer within the PiP structure to form the landing surface for mounting a memory component analogous to PoP architecture.

FiPoP is architecturally similar to PoP construction yet is achievable using different technologies such as fan-out WLP. FiPoP is a case of “architectural convergence” within the domain of traditional packaging technology for mobile platforms ahead of the more radical paradigm of through silicon via (TSV) and wafer scale 3D integration which is separately in the making.


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Raj Pendse, Ph.D. VP, Emerging Technologies, may be contacted at STATS ChipPAC Inc. 47400 Kato Road, Fremont, CA 94538; 510-979-833; E-mail: Raj.pendse@statschippac.com