Issue



Laminated Housing Technology


10/01/2008







Traditional socket manufacturing methods are limited in the ability to meet contact methods of the test socket market, especially those related to semiconductor packages. Rather than machined or molded housings, a layered laminate methodology is proving to break through these limitations.

BY GREG SPANIER, Cascade Microtech Gryphics Product Group

The test socket market is continually driving to smaller, more robust, electrically invisible contact methods. A critical limitation to achieving these objectives is the machined or molded socket housing and the manufacturing methods used to fabricate them.

Some of the drawbacks to machining socket housings are the limits that can be achieved in feature sizes, the capacity constraints that can occur when large feature counts are necessary, achieving stringent flatness/warpage specifications for larger arrays, and maintaining consistent feature tolerances. As the feature requirements get smaller, hole diameter-to-depth aspect ratio becomes a limitation. Some options exist to solve this challenge. The housing can be separated into multiple layers, slower machining processes such as peck drilling can be used, or expensive custom tools and equipment are required. Additionally, a substantial amount of the machinist’s time can be spent deburring each part with an increased risk to quality as the feature sizes get smaller. In a large array of holes, it can be difficult to ensure that all cavities are free of debris. Another limit is feature shape. The limits of machining often require approximating shapes by using round holes. Depending on the nature of the interconnect technology, you are literally left putting a square peg in a round hole. With this method of housing manufacturing, all these factors can lead to a higher cost of ownership (Figure 1).


Figure 1. Machined housing with thin webs.
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Many factors are considered prior to deciding to mold a socket housing. For high-volume, cost-sensitive applications, molding is the manufacturing method-of-choice due to its lower piece part price, increased capacity, and overall quality. When the applications volume requirements warrant molding the housing, the tooling charges can be cost prohibitive. This also may be the case for large area array semiconductor packages. Large arrays on smaller pitches require thin wall sections. Filling these walls in a mold becomes challenging. For applications that require solder reflow to a PCB, flatness/warpage concerns arise particularly at the higher reflow temperatures required for lead-free solders. Flexibility is another limitation. Semiconductor packages and package families may require tooling for each package or package family. Tooling costs, lead times, tooling flexibility all lead to a higher cost of ownership with this method of housing manufacture.

Layered Laminated Socket Housings

A new socket housing manufacturing methodology has been developed* to address the limitations in machining and molding, with the addition of unique feature design capabilities. This layering and laminating (LL) technique leverages PCB industry processes into socket housing design and fabrication. The LL socket housing methodology supports both low- and high-volume applications cost effectively. The simple and proven processes yield shorter lead times, allowing custom packages as well as high-volume orders required for applications including reliability testing.

LL housings are constructed of multiple layers of polyimide material. Each layer has geometric features laser cut, punched, or drilled into it. Depending on the assembly stack up of the layers, these features could be circular, rectangular or conceivably any shape that can be cut using current laser cutting or punching technologies. Each feature has a specific function as it relates to the socket contact. The lower section of the LL housing is typically used to retain the contact and, therefore, has a contact retention function. It also positions the contact to the PCB, and thus must provide precise contact location. The center section of the LL housing is typically clearance to the contact and adds spacing for overall height. The top section may add contact positional control and, for BGA devices, package ball alignment to the contacts (Figure 2).


Figure 2. Cross section of a LL housing showing larger center section not achievable through molding or machining.
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LL housing construction offers a number of performance improvements over machining and molding. The polyimide material offers a lower dielectric constant than typical materials such as Torlon, Peek, Ultem, and Vespel, allowing improvements in the electrical performance of the socket. Conceivably, since the LL process is very similar to PCB construction, metal layers could be added to shield individual or groups of contacts resulting in higher electrical performance. When a contact’s geometry requires a larger center section than the top or bottom layers, molded and/or machined housings must be broken into 2 pieces that will fit together, capturing the contact between them. Based on the lamination process, the LL housing can have a larger center opening than the outer layer openings and still be laminated into one housing, thus eliminating the two-piece housing. The relative stability of the lamination process ensures that tight flatness/warpage specifications can be achieved. The polyimide material is well-known in the industry and profiled through solder reflow processes. Housings can be fabricated either one up for small volumes (<10) or patterned onto a panel and laminated multi-up (Figure 3) to support higher volume applications. The LL process eliminates the necessity to machine housings at the lower volumes at higher cost and wait for the tooling to be completed for high volume. The LL process can support low-volume requirements for engineering development and be ramped up quickly to support high volumes necessary for product reliability testing and qualification. Both applications would only require one socket type and with significantly shorter lead times and cost-of-ownership (COO).


Figure 3. Multi-up laminated panel with 32 housings.
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Whether its a quick-turn socket to test packaged silicon, or a burn-in socket without the long lead time associated with the tooling, the LL housing socket technology eliminates development headaches. LL housing sockets offer improved electrical performance allowing the development focus to be on silicon and package verification. These housings do not require large tooling investment to support development through reliability testing. They also offer a lower cost of ownership from development through reliability for semiconductor test.

*Cascade Microtech, Inc. Gryphics Product Group


GREG SPANIER, director, product marketing and applications, may be contacted at Cascade Microtech, Inc., Gryphics Products Group, 3850 Annapolis Lane Suite 140, Plymouth, MN 55447; 763/509-0066 Email:greg.spanier@cmicro.com