Thin, Strong, Cheap
Improving 3D Chip quality by Remote Cold Dry Etching
BY PETER HEINZE, PH.D., MARTIN AMBERGER, AND THERESE CHABERT, PVA TEPLA
As 3D interconnection focuses on chip thicknesses at 50 µm and below, and next-generation memory chip and chip card requirements become more specific, the need for both ultra-thin and stable silicon chips has become evident. While some thinning approaches <50 µm focus on expensive rigid carrier systems with bonding- and de-bonding processes that include special consumables and consequently many additional process steps, others are focusing on how to achieve cost reduction along with improved chip properties within the conventional production environment using given standard consumables, like tapes. It becomes apparent that in the end, thin but strong chips — and not bonded wafers — are to be assembled in chip packages, so the die singulation process has to be taken into account from the very beginning. Kroeninger et al. (2001) were among the first to emphasize the benefit of healing chip side walls.1 The need for doing this has been expressed for the first time in the 2007 ITRS roadmap, which states that wafer singulation is another key technology to retaining die strength, and that singulation methods including new laser cut methods or plasma etching will be required.
Chip Side Healing, Dicing by Etching, Advanced Etch Separation
The singulation market is dominated by blade and laser dicing. Both are searching for the best technique to singulate thin wafers. Blade dicing can be optimized, for example, by varying wheel RPM, dicing speed, grain size, blade width, dual-cut depth, etc. Because front-side chipping can never be avoided, the chip front side damage can measure up to 10 µm. In production, back-side chipping after full-cut dicing can easily be 20-35 µm on each chip side. At dies 30 µm and below, the dicing saw slows down, trying not to bend the wafer and compress the dicing tape while squeezing the chips to destruction. Here, the laser gains momentum by both cutting speed and no mechanical chip breaking. However, the heat affected zone (HAZ), with its depth of ~5-15 µm, has a strong negative impact on die strength and must be eliminated. In addition, the Hamamatsu mechanical stress-inducing singulation technology — based on IR-laser transferring mono-crystalline material into poly-crystalline silicon along the horizontal neutral wafer plane — weakens the crystal lattice and therefore diminishes the die strength as well.
As a rule-of-thumb for any mono-crystalline material like silicon: after physical damage by wafer thinning or die separation (laser or blade), chemical surface treatment to remove the damaged zone is required to regain original material strength. After laser or blade dicing without chip side healing, chips do not differ greatly in terms of die strength on a very low level. Based on the 3- and 4-point breaking tool, characteristic die strength (CDS = 63.2% probability of breakage in Weibull-Diagram) varies at best around 530-580 MPa. However, when singulation injuries at the chip sides (front- and back-side chipping, or HAZ) are completely eliminated, die strength improves, and die strength of more than 1500 MPa can be achieved.2 The yield relevant minimum die strength (MDS = 1% probability of breakage in Weibull-Diagram) improves from 200-300 MPa to up to 1200 MPa, which equals an increase of up to 500%. Since die strength measurement is a sensitive task from the methodological point of view, the relative changes of flexural stress within a given design of experiment are important.3
Having eliminated chip side damage even more, die properties upon mechanical load can be evaluated. After chip side healing (CSH), the comparison of normal and reverse die bending makes it possible to distinguish between the relative impact on die strength dominated by backside treatment and front-end chip manufacturing process. The front-end chip design influence on die strength can be determined, and therefore optimized.
The thinner the chip, the more the die strength is influenced by damage to the die edge.4 Consequently, CSH becomes inevitable so ultra-thin chips can resist against thermal and mechanical stress downstream during back-end assembly processes. In comparison, when subjected to the 3-Point and Ball ring die breaking method, the relative impact of the die edge increased by ~110% while the thickness was reduced from 75 to 50 µm.
Table 1. Summary of three advanced wafer separation methods to avoid chip-side damage.
Three novel pre-assembly process flows, focused at the die edge to produce wafer singulation with minimum silicon damage and loss of die strength, include CSH and its derivates, dicing by etching (DbE), and advanced etch separation (AES) (Table 1). From CSH via DbE to AES, each process character shifts from side-wall stress relief to more singulation purpose, ending in an optional thinning application.
Chip Side Healing (CSH)
The work flow of the CSH process is shown in Figure 1. The CSH process can be retrofitted to an existing blade or laser dicing process to regain the material strength of silicon chips after singulation. The results of the CSH method have been presented in detail in Heinze et al. 2007.5
Dicing by Etching (DbE)
DbE (Figure 1) is presented for doing both final singulation as well as CSH, where a blade (or laser) first cuts through the metal lines and low-k as a partial cut step. This kind of deep groove can be tolerated better by thin, delicate wafers than a full cut, which would easily destroy the chip backside due to heavy chipping.
Figure 1. The Pre-assembly process flow for chip-side healing (CSH) and dicing-by-etching (DbE). If step # 7 is a partial cut, the process is called DbE.
Figure 2. Die edge profiles. left: DbE, active die side up. right: Advanced etch separation (AES), active side down.
Therefore, DbE acts as the final soft singulation step, with no chipping or other mechanical damage along the kerf left behind by the blade. Figure 2 (left side) shows the die edge profile after DbE. Dicing speed reaches 20 µm/min on the 300-mm wafer. In combination with the high-speed partial cut, the singulation throughput and yield should be increased by DbE.
Advanced Etch Separation (AES)
Whereas CSH is a method to recover die strength, and DbE improves the partial blade cut and contributes to singulation, AES technology focuses on both separation and die thinning, with effective cost reduction for 3D-IC manufacturing as the final goal. Because dicing before brinding (DBG) singulates by grinding , a 3-5 µm-thick glue bead is generated around the front side of each die to prevents any front-side chipping removal by dry etching. 6 The reverse-bending test shows a zero die strength improvement.
Figure 3. AES process for thin chip manufacturing including 3D-TSV.
The AES process requires neither a protective coating, nor hard carrier bonding and de-bonding, nor special consumables or tapes; but is based on two simple changes in the current pre-assembly process flow. It provides perfectly healed chips with extreme bending capability and highest possible die strength (Figure 3).7 Due to the lack of additional material like hardcarrier and bonding glue their additional total thickness variations (TTV) are eliminated which can become important at final die thicknesses <20 µm.
After a partial cut is made in the full wafer, for depth control as well as dicing speed at minimum blade consumption, the wafer is not singulated by grinding. The wafer integrity is not affected and no single die movement can occur with its consequential partial embedding into the glue. Rather, the backgrinding tape is peeled off and a dicing taped frame is mounted to the same active side on the same chuck. From here on, standard dicing frames are handled instead of thin wafers or chips, respectively. At the end of the AES-process, the thin dies are on the same standard carrier ready for flip-picking. The active side is protected by tape at all times. Figure 2 (right side) shows the die-edge profile after the AES process. On the fly, the 3D-TSV (Figure 4) can protrude by recess-etching without been pressed into silicon due to lack of mechanical friction or down-force impact.*
Temporary bonding, de-bonding, thinning and dicing contribute about 12% to the 3D-TSV manufacturing budget.8 The AES process addresses this part of the cost in 3D-TSV. Cost issues and chip stability are problems for 3D-TSV and need to be be addressed to secure the future of 3D-TSV. Thermal budget and stress in 3D-stacks is a serious yield issue. Stronger chips will positively contribute to this technology approach.
Applying the newly developed technology based on remote cold dry stress relief, thinning, and singulation is possible. By this method, new wafer and chip handling concepts on dicing frame allow for cost reduction combined with safe handling of the thinnest chips, and is also applicable for 3D-TSV manufacturing and assembly.
*PVA TePla has applied for a patent for the AES-process.
- Kroenninger, W. et al. (2001): The Stability of Silicon Chips. Proceedings of Fraunhofer Gesellschaft FhG workshop . Thin Semiconductor Devices-Manufacturing and Applications 2001, Munich.
- Heinze,P., Amberger, M., Chabert, T. (2008 a): Perfect Chips: Chip-Side-Wall Stress Relief Boosts Stability. Future Fab International #25 (April 2008), p. 111-117.
- Stephan Schoenfelder, Matthias Ebert, Christof Landesberger, Karlheinz Bock (2006): Investigations of the Influence of Dicing Techniques on the Strength Properties of Thin Silicon. Microelectronics Reliability, May 2006
- Application Note: CSH, Stress Relief of Thin Chip Sides. PVA TePla, Munich, June 2007.
- Heinze,P., Amberger, M., Chabert, T. (2007): Five-Side Stress Relief - The method to get the “Perfect Die”. Advanced Packaging Conference-0ctober 10-11, 2007 SEMICON Europa 2007 - Stuttgart, Germany.
- Heinze,P., Amberger, M., Chabert, T. (2008 b): So macht man den Perfekten Chip. Mikroproduction 1/2008, p. 45-50.
7. Heinze,P., Amberger, M., Chabert, T. (2008 c): Thin Chips for 3D-TSV at Ultra-low Cost. Future Fab International #26 (July 2008).
- Mounier, E. (2007): Trends in 3D Wafer Level Advanced Packaging. Advanced Packaging Conference-0ctober 10-11, 2007 SEMICON Europa 2007 - Stuttgart, Germany.
PETER HEINZE, Ph.D, director pre-assembly; MARTIN AMBERGER, manager technology and application, and THERESE CHABERT, senior application engineer, may be contacted at PVA TePla AG, Hans-Reidl-Strasse 5, D-85622, Feldkirchen, Germany; 49 89 905 03-180; E-mail: email@example.com