Enabling Cooling Strategies for 3D packages
Riding on recent advances in nano-fabrication technology, thin-film thermoelectric coolers (TF-TEC) have been developed with active material as thin as 10-20 ??m. These TF-TECs have demonstrated as much as 30?? higher power pumping capabilities per unit area as compared to conventional thermoelectric modules, while achieving a maximum temperature difference of 60??C. A single TF-TEC element as small as 600 ?? 600 ?? 100 µm high, can pump a maximum power of more than 0.5 W. These elements can be placed into arrays with varying densities, or packing fractions, to achieve different levels of performance.
Thin-film thermoelectric cooling, in the form of the thermal copper pillar bump (TCPB), is proposed as an alternative approach for thermal management of high-performance devices, as well as 3D chip stacks. Until now, 3D package cooling has focused on optimizing internal heat dissipation paths. This effort includes temperature-aware physical design tools, thermal via insertion, and 3D IC micro-channel cooling techniques. In addition to offering unprecedented performance advantages, TF-TECs, lend themselves to more flexible design architectures than conventional thermoelectric elements. This enables unique, chip-level integration of active cooling, offering novel cooling strategies for 3D chip stacks.
The TCPB is a thermoelectric device made from thin-film thermoelectric material. This material is embedded into flip-chip interconnects which are based on copper pillar technology for use in electronics and optoelectronic packaging. Unlike conventional solder bumps that provide an electrical and mechanical functionality for the package, thermal bumps act as solid-state heat pumps and add a thermal management functionality locally on the surface of a chip. The stack-up of a thermal bump, including the thin-film material, solder and electrical traces, is only 100-??m high and has a diameter of 238 ??m.
The thermal bump was developed* as a method for integrating active thermal management functionality at the chip level in the same manner that transistors, resistors, and capacitors are integrated in conventional circuit designs today. The copper pillar bump was selected as an integration strategy due to its widespread acceptance by Intel, Amkor, and others as the method for connecting microprocessors and other advanced electronics devices to various surfaces during flip chip packaging. Thermal bumps can be integrated into discrete devices or as a part of the standard flip chip process.
3D ICs provide an attractive solution for improving circuit performance and allowing for further reduction in the form factor of semiconductor devices. Such solutions, however, are expected to generate a significantly greater amount of heat per unit area than its 2D counter-part, and therefore will exacerbate existing thermal problems increasing both the average and peak power densities.
Figure 1. Cooling of 3D ICs with thermal bumps.
Thermal bumps are proposed for removing heat from 3D ICs in all three directions including traditional back-side of the die, the lateral side, and the active or front side of a 3D IC (Figure 1).
Back-side cooling can be enhanced by the introduction of thermal bumps either into the heatsink to form an active heatsink, or into the heat spreader. This is behind the first level or TIM one (thermal interface material).
For a 3D chip stack, lateral heat removal can be combined with an interposer through which the heat can be removed. Here, the thermoelectric material is to the side or underneath the substrate, and the heat is pulled from the center segment to the side.
The last concept is active-side cooling. Here, the active side of the CPU is flip chip attached with thermal bumps replacing some of the conventional copper pillar bumps.
The thermal bump enables a new generation of electronic product design by including chip and module-level thermal management directly into the packaging process and opens the door to chip-level thermal management for traditional and now 3D products.
* Nextreme Thermal Solutions
SERI LEE, Ph. D. CTO, may be contacted at Nextreme Thermal Solutions, 3908 Patriot Dr. Suite 140, Durham, NC. 27703; 919/485-5509; E-mail: slee&nextreme.com