Solder Joint Reliability of High-end FCSiP
BY SANG HA KIM, AND HAN PARK, NEC ELECTRONICS AMERICA; AnD CHIKA KAKEGAWA, HIROSHI TABUCHI, MAMORU KAJIHARA, NEC ELECTRONICS CORP.
Challenges of high-end FCSiP include routability with acceptable signal and power integrity, package thermo-mechanical behaviors, and long term reliability performance. Data obtained from DOE analysis and an FEA case study defined critical factors to FCSiP solder joint fatigue and how to address them.
The development of high-density interconnection package has become important in fast-growing electronic industries such as server, network, and telecommunication applications. The flip chip system-in-package (FCSiP) can conduct higher electrical performance, reduce the size of system board, and also reduce the layer count in the system board by combining the advantages of flip chip and SiP technology.
Figure 1. FCSiP configuration, a. topside view (without heat spreader) and b. cross section view.
The FCSiP consists of one ASIC flip chip centered on the package, and four PBGA memory packages at the four corners of the SiP module (Figure 1). Flip chip ASIC and memory configuration in SiP requires fast operating frequency and higher bandwidth. The challenges of high-end FCSiP are routability with acceptable signal and power integrity, package thermo-mechanical behaviors, and long-term reliability performance.
A design of experiments (DOE) analysis was used to carry out finite element analaysis (FEA case studies) and predict optimized FCSiP construction and assembly material sets. A set of FEA models whose strain energy density had been calculated prior to the testing was used. The analysis was done with a set of models based on evaluation factors and levels.
To optimize the construction process and the combinations of the materials, the fatigue lifetime of the BGA solder joint was evaluated based on 2-D Anand’s visco-plastic non-linear model. A total of 8 runs were performed with the 2(5-2) ¼ partial factorial design of DOE. The reference temperature was set at 183??C as the stress-free point, and the thermal cycling test range used for the simulation was 0??C to 100??C.
According to statistical analysis, the materials used for underfill and the heat spreader were critical to the 2nd (PBGA to SiP substrate) and 3rd level (SiP to board) solder joint lifetime, respectively. To improve the reliability of the memory PBGA package solder joint, the implementation of high Tg underfill material is required. In addition, analysis of variance (ANOVA) results indicated that the heat spreader was a dominant factor in affecting SiP solder joint reliability.
Improving the solder joint lifetime and developing a package assembly process for FCSiP were major concerns. After considering productivity and process workability, it was possible to change the construction and material sets for the SiP module. The optimized FCSiP samples were evaluated through FEA case study and accelerated thermal cycling (ATC) test.
Solder Joint Lifetime Analysis
Based on the optimized FCSiP construction and material sets, another FEA case study addressed solder joint lifetime and critical area of the fatigue failure. Figure 2 shows FEA result of the maximum visco-plastic energy density on the 8th solder ball from the center. The maximum visco-plastic energy occurred at the edge of the flip chip due to the mismatch of coefficient of thermal expansion (CTE), indicating that energy tends to intensify near the solder balls at the flip chip edge.
Figure 2. Fatigue lifetime of SiP solder joint. (Red: optimized, Blue: sample)
Experimental Procedure and Result
Three different test vehicles were tested using ATC. The ATC test condition was set to comply with IPC-9701 standard (0??C to 100??C temperature cycle, 10??C/minute ramp up and cool down rate, 10minute dwell time at 0??C and 100??C). In-situ event detectors monitored the continuity of the daisy chains on the test vehicle.4 The daisy chain test vehicles were continuously monitored by an event detector at a resolution of 0.2 ??sec. When the resistance of the daisy chain net exceeds 1000 W, the real-time monitoring system records an event. The cycle to failure was defined by the number of thermal cycles which occurred at the first verified event.5
The test vehicle used a 1.0-mm pitch FCSiP on bismaleimide triazine (BT) resin substrate, and had 2803 I/O with a body size of 55 mm ?? 55 mm. The BT substrate was made with 10 metal layers (3-4-3 high density build up) with a thickness of 1.8 mm.
Three SiP lots were assembled and tested sequentially. The first lot with 0.5-mm Cu heat spreader and the second lot with 1.0-mm Cu heat spreader were mounted on 125-mil thickness test boards without external heatsinks, respectively. The objective of the first 2 ATC lots was to investigate the impact of heat spreader thickness on solder joint fatigue lifetime.
In addition, the third lot was implemented with external heatsink on 1.0-mm Cu heat spreader by using a mechanical clamp. The purpose of the third ATC lot was to investigate the impact of external heatsink attachment on solder joint reliability performance. The first lot consists of 15 SiP components and the other two lots consisted of 32 SiP components.
ATC Experiment Result
For the first ATC lot with 0.5-mm heat spreader, all 15 samples recorded failures after ATC testing terminated at 3,700 cycles. For the second ATC lot with 1.0-mm heat spreader without external heat sink, 27 out of 32 samples recorded failures after ATC testing terminated at 3,704 cycles. For the third ATC lot with an external heatsink and 1.0-mm heat spreader, 29 out of 32 samples recorded failures after ATC testing terminated at 3,710 cycles.
Figure 3. Weibull plot of three FCSiP ATC lots.
The first fatigue failures of the second and third ATC lot were 2,169 cycles and 2,110 cycles, respectively. The failure data for three ATC lots were fit to Weibull distributions (Figure 3).
As expected from FEA case study, a thicker heat spreader improved solder joint lifetime by approximately 15% compared with that of a thinner heat spreader. In addition, no significant difference of solder joint lifetime with heatsinks implementation. ATC experiment data was well correlated with the previous FEA results.
ATC Failure Analysis Result
The results of dye penetration tests revealed that SiP solder joint fatigue failures were distributed around the edge of ASIC flip chip, a high stress concentration area. Cross-section analysis result revealed no failure at flip chip bump and PBGA solder joint. However, SiP BGA solder joint failure was found based on cross-section analysis result as shown in Figure 4. The failure locations matched each other.
Figure 4. FA result, cross-section result of 2nd lot at 3000 cyc.
According to the data obtained from DOE analysis, critical factors to FCSiP solder joint fatigue lifetime were selected and the optimization process for FCSiP construction and material sets were carried out. FEA case study result defined the edge of the flip chip as the critical region and this result correlated with the actual ATC test results. In addition, a thicker heat spreader proved to improve the solder joint fatigue lifetime. However, external heat sink implementation proved not to be critical to the solder joint fatigue.
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SANG HA KIM, staff packaging engineer, and and HAN PARK, senior engineering manager, may be contacted at NEC Electronics America, 2880 Scott Blvd, Santa Clara, CA 95050;408/588-6238; E-mail: firstname.lastname@example.org.