Embedding Technologies for SiP Manufacturing



Following the path of electronics evolution, many technological concepts such as system-in-package (SiP), system-on-chip (SoC), and stacked chip packaging have drawn exploration roadmaps for higher system integration. Current technologies provide organic substrates with high-density build-up layers and micro-vias, equipped on both sides with surface mount passive components and active chips in packages. The lateral space shrink of active components on a board has been further achieved by using CSPs, flip chips, or stacked chips connected to an interposer substrate or lead frame by bond wires. Many novelties have led to a progressive evolution of the 2D-SiPs to a 3D build up, or 3D-SiP. Nevertheless, further miniaturization in 3D-SiPs is required and can be achieved by 3-D integration of components.

System requirements for signal frequencies in the order of several GHz can not be met by long bond wires and extensive interconnect paths on a board. To maintain signal integrity, much shorter and impedance-matched interconnects are required. Embedding technologies of passive and active components have come dynamically into play to lead the way towards highly miniaturized 3D-SiPs. A number of different embedding approaches have been presented in the past.1 Among the most recent technologies, the integrated module board (IMB) technology was developed by Helsinki University of Technology, in which chips are embedded in cavities into the core substrate.2 Industrialization plans for the IMB technology are being pursued.

Figure 1. In CiP, electrical contacts are realized by laser-drilled and metallized micro-vias.
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Fraunhofer IZM, in collaboration with Technical University of Berlin has developed the chip-in-polymer technology (CiP) for embedding active chips for SiP applications. Significant developments of the technology have taken place in the framework of an EU-funded project, HIDING DIES, where active components were embedded by lamination of resin-coated-copper (RCCs) layers.3 The basic concept involves embedding thin chips into build-up layers using well-established PCB technology. Electrical contacts to the chips are realized by laser-drilled and metallized micro-vias (Figure 1). As part of the HIDING DIES Project, Fraunhofer IZM has further developed generic CiP technology to offer versatile solutions for the realization of 3D-SiP modules. Another embedding approach involves embedding a flip chip with very thin bumps into build-up layers.4

CiP Technology

Wafer preparation. Laser drilling of micro-vias and the PCB metallization process is not compatible with contact pads of semiconductor chips. Therefore, another layer of 5-µm Cu is applied to the bond pads of the chips being embedded. Wafers are thinned up to 50 µm. The present technology can handle contact pitches up to 150 µm by forming micro-vias directly to the chip pads. Prototype work has extended up to 100-µm peripheral pad pitch.

Chip placement and bonding. Placement accuracy is extremely crucial for chip embedding. Placement accuracy of ??10 µm at 3s was achieved on 18"??12" panels with a placement speed of 1000 components/h. Chip bonding has been developed using printable pastes and die-attach films (DAF).

Embedding by RCC lamination. The core substrate with die bonded chips is covered on both sides with an RCC layer. Temperature and pressure profiles should be adjusted carefully to promote epoxy adhesion at all interfaces and avoid chip breakage. For the embedding of 50-µm chips, 90-µm epoxy RCC with 5-µm Cu has been used resulting in a desirable thickness of 15-20 µm over the chip surface. A 35-µm Cu protection layer is peeled off after vacuum lamination. Epoxy curing takes place at about 175??C for 60 minutes. The HIDING DIES project successfully demonstrated multi-chip embedding up to 2 chip stacks. As part of a new initiative, the HERMES project, embedding of 4-chip stacks will be attempted for higher 3D integration.

Figure 2. Nearly complete micro-via filling can be achieved wih special Cu chemistry.
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Via laser drilling and metallization. Laser drilling vias to the bond pads of embedded chips is comparable to the established formation of micro-vias on PCBs. A pulsed 355-nm UV laser, which can ablate Cu as well as the RCC dielectric, has been used. With the current I/O pad pitch (min. 150 µm) and enlarged Cu pads, alignment based on fiducials on 10??10 cm2 sub-panels is sufficient. After drilling, the micro-vias are chemically cleaned and then treated by a Pd activation and electroless Cu deposition. The Cu layer is approximately 0.5-µm thick, and acts as a seed layer for the subsequent Cu electroplating. A minimum thickness of 10-µm Cu is required in micro-vias. By the use of special Cu plating chemistry, a nearly complete filling of the micro-vias can be achieved (Figure 2).

Figure 3. Process sequence for novel power MOSFET package.
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Copper structuring. The top interconnection pattern is structured by a maskless process based on laser structuring. First, a Sn layer of 1-µm thickness is applied by an immersion process. The conductor design is written into the Sn by laser ablation. The remaining Sn is then used as an etch mask. By subtractive process, the Cu is etched and the Sn mask layer is stripped. A view on the final structure of an embedded chip with interconnects on top is shown in Figure 3. In HIDING DIES, 50-µm Cu interconnect lines have been structured. Recently, laser direct imaging (LDI) with a wavelength of 355 nm has been used, completely bypassing the Sn etch mask. In the HERMES project, a target of 15-25 µm interconnect lines has been set and a semi-additive structuring process will be pursued.

Reliability of Embedded Chips

Reliability tests performed included temperature storage 125 ??C for 1000 h; air-to-air thermal shock -55??C / +125??C, 6000 cycles; and humidity storage 85??C / 85% relative humidity, 2000 h. All tests were passed without opens or degradation of daisy chain resistances, and cross-sections did not show degradations like delamination. Samples were also tested according to JEDEC level 3, i. e. 168 h at 30??C and 60 % rel. humidity followed by 3 reflows at 260 ??C peak temperature (lead-free condition) and JEDEC level 1 (168 h at 85??C and 85% rel. humidity pre-conditioning) resulting in no delaminations. Besides the experimental assessment of reliability, an extensive 3D FEM modeling and simulation of thermomechanical behavior of embedded chips was performed.6 These simulations did not reveal critical points in CiP packages.

System-in-Package Applications

The main application of CiP technology is expected to be in the manufacturing of small packages like stackable chip packages, 3D-SiPs, or small modules with only a few chips. The chips should be tested before embedding because repair is not possible.

Figure 4. Embedded power MOSFET chip.
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Chip Card Module. In the framework of HIDING DIES, the first functional device realized was a chip card module. It contains a chip with 3.2 ?? 2.9 mm2 size and 10 connected contacts. The 50-µm chips were bonded on a 100-µm FR4 core, then a 80-µm dielectric / 5-µm Cu RCC was laminated on both sides, yielding a module with 4 Cu layers. The total module thickness is about 300 µm. The functionality of the controller chips was successfully tested after module manufacturing. The functional chip card module is shown in Figure 4; the further steps of micro-via opening and Cu deposition with subsequent structuring are also shown.

Figure 5. Concept of 4-chip multilevel embedding for realization of 3D-SiPs.
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Power MOSFET Module. Fraunhofer IZM has internally developed a low-cost package technology for power MOSFET chips. The chips are designed to switch currents of at least 80 Å and have a size of 6 ?? 6 mm2 and a thickness of 200 µm, determined by the thickness of the chips available. Their I/Os are Al contacts for gate and source at the top and a solderable contact with Ag finish for drain at the bottom. The basic strategy for the project was to generate a SMD package for power chips, kept as simple and thin as possible. Therefore no core substrate was used. Instead the chips were soldered by their drain contact (backside) to a 36-µm Cu foil. Then the chips were embedded by lamination, micro-vias were drilled to gate and source, and through-vias were drilled from top Cu layer to the bottom substrate Cu layer. The process sequence is shown in Figure 5.7 The resultant module thickness is slightly thicker than the chips and has a size of only 3.3??3.3 mm2.


The HIDING DIES project has successfully shown technological capabilities of chip embedding for miniaturized electronic systems and has sparked interest for industrial adoption. The HERMES project, with wide participation of European industries and research institutes, was launched in May 2008 to address these industrialization issues. It will focus mainly on industrial adaptation of embedding technologies with an additional scope of furthering also the existing technological capabilities at prototype level. In this context, conceptual designs of embedding 4-level chip stacks will be explored for even higher integration in 3D-SiPs.


  1. S. Norlyng, “Integrated component technologies: Opportunities, economics and trends”, IMAPS Nordic, October 2003.
  2. T. Waris, R. Tuominen, J. Kivilahti, “Panel-sized integrated module board manufacturing”, Proc. Polytronics Conference, Oct. 21-24, 2001, Potsdam.
  3. A. Ostmann, A. Neumann, P. Sommer, H. Reichl, “Buried components in printed circuit boards”, Advancing Microelectronics, May/June 2005, pp. 13-18.
  4. A. Ostmann, D. Manessis, A. Neumann, H. Reichl, “Lamination technology for system-in-package manufacturing”, Proc. Microtech 2007-IMAPS UK, 6-7 March, 2007, UK.
  5. D. Manessis, S-F.Yen, A. Ostmann, R. Aschenbrenner and H. Reichl, “Technical Understanding of resin-Coated-Copper (RCC) lamination processes for realisation of reliable chip embedding technologies”, Proc. in Electronics Components & Technology Conference (ECTC) 2007, Reno, NV, May 29-June 1, 2007, pp. 278-285.
  6. J.-P. Sommer, B. Michel, A. Ostmann, “ Electronic Assemblies with Hidden Dies ??? Design Support by Means of FE Analysis “, Proc. ESTC Conference, September 5-7, 2006, Dresden, Germany.
  7. L. Boettcher, A. Ostmann, D. Manessis, H. Reichl, “Through silicon via interconnection enabling 3D wafer-level SIP ”, Proc. SMTA International, September 2007, Orlando, pp. 15-22.

DIONYSIOS MANESSIS, Ph.D., principal technology scientist, and ANDREAS OSTMANN, manager, embedding and substrate technologies group, may be contacted Fraunhofer IZM, Gustav-Meyer-Allee 25, 13355 Berlin, Germany; +49 30 46403229; E-mail:;