Issue



Extending Leadframe Application Opportunities


05/01/2008







BY LEE SMITH, Amkor Technology

Leadframe-based packages accounted for over 70% of the 147 billion IC packages produced in 2007. The quad flat no lead (QFN) and quad flat pack (QFP) are two of the fastest growing leadframe package families. As proof that there are still opportunities to innovate in this sector, a novel leadframe-based technology* was developed; incorporating QFN and QFP technologies by integrating inner lands within a standard exposed pad QFP package outline.

Managing silicon performance increases in a low cost package platform were the key development challenges. The solution fuses QFN and QFP technologies to extend pin-count capability or increase I/O density of leadframe packaging. The resulting platform provides double the I/O within a current QFP footprint, or 50% reduction in body size for an existing lead count. However, the electrical and thermal performance it offers enables designers to design devices into a low-cost leadframe platform that can meet the size and performance requirements that historically would have to be addressed by a custom PBGA package. This technology’s design flexibility in signal, power, and ground-pin optimization, coupled with the thermal benefits of exposed-pad technology enable the package to serve high speed or RF applications up to 10 gigabits/second, or 10 GHz, and dissipate over 4 watts of power.


Isometric and cross section views of a complete leadframe-based package.
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System-level and IC designers require a range of features to support higher I/O, power, and ground-pin-count densities. These package design challenges increase as designers take advantage of the higher integration available in 65- and 45-nm CMOS. As such, this platform’s design features include lead counts approaching 400 pins with roadmap to higher pin counts, a 10??10-mm to 24 ??24-mm body size, low profile, lead-free material sets, and uses standard SMT assembly and rework.

Low-cost manufacturing is achieved by using the same process technologies as high volume QFP and QFN packages. The package is based on a copper leadframe produced by either stamping or etching, plated with either silver spot or overall NiPdAu finish. Either plating provides a wire-bondable surface, while the overall NiPdAu plating provides solderable leads and lands that eliminate the need for subsequent lead finish plating during the assembly process. Figure 1 shows the top and bottom as well as cross sectional views of a finished package.

This package format is ideal for most IC technologies including digital, mixed signal or RF CMOS, providing an option to stay in or revert back to a leadframe platform for SoC, micro controller, ASIC, or DSP devices that are at, or have exceeded, the pin-count or performance capabilities of leadframe technology. This technology is particularly well-suited for applications requiring superior electrical or thermal performance in a cost-constrained environment including hard disk drives, notebook PCs, Ethernet communication, digital television, data conversion and many others.

Conclusion

This innovation extends leadframe technology into the pin-count and performance range of BGAs without requiring major changes in industry infrastructure. Technical and manufacturing breakthroughs over the past few years of development led to creation of a novel package that is poised to extend cost-effective leadframe based technology into a host of new applications. Package outline mechanical standardization has been initiated within JEDEC. Test contactors are available, and infrastructure will continue to expand as market momentum for this platform accelerates.

*FusionQuad from Amkor Technologies


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LEE SMITH, V.P of business development, may be contacted at Amkor Technolgoy, 1900 South Price Rd., Chandler, AZ 85248; 480/821-5000; lsmit@amkor.com.