Diversity and Standards


3D packaging has a bright future. It simply makes a lot of sense. So, being an equipment supplier, the next question is: what opportunities does 3D packaging offer for the equipment industry?

In fact, the third dimension not only increases package density but also adds a diversity of new package designs. New, or at least modified, process techniques will be required. This certainly offers new opportunities for equipment suppliers. But diversity and opportunities alone do not generate good business, in the end, standards are needed to drive the economy of scale.

Through silicon vias, (TSVs) have become the Holy Grail of ultimate 3-D interconnect. TSVs offer opportunities for DRIE, laser drill, and plating equipment makers to optimize their products and drive TSV yield up and cost down. But what about photo-lithography? Does current equipment satisfy the requirements for 3D packaging? There is more involved than just TSVs.

Image sensors are interesting products to consider. Wafer-level packaging (WLP) of image sensors includes several common characteristics of 3D packaging such as TSVs, redistribution layers (RDL) on the back side of the wafer, and wafer-level assembly. Additionally, they are early adopters of 3D packaging processes.

Specific requirements for photo-lithography equipment include the need for back-side-lithography – an equipment option previously not required for WLP – and conformal coating of TSVs with photo resist and organic dielectrics. Equipment manufacturers are familiar with these requirements from the MEMS industry, and have developed bottom-side-alignment systems and spray-coating equipment. Now these equipment options are needed on 300-mm equipment.

Image sensor stacks and optics are assembled at the wafer level using wafer bonding. Economics of this technology is attractive, especially for small die. Moreover, with a wafer-level lens replication technique, the cost of manufacturing image sensors can be further reduced.

3D packaging requires processes on the back side of very thin wafers. Currently, for wire-bonded 3D packages, back-side processes are more or less limited to stress-relief and dicing. Many of the more advanced 3D packages will require processes such as sputtering, DRIE, electroplating, and photolithography on very thin wafers. That’s why thin wafer handing has become so critical. In this respect, image sensor packaging is different: although image sensor wafers are thinned to less than 100-??m thickness, they are permanently bonded to glass carriers prior to thinning, which allows them to be handled in standard semiconductor equipment. Even after dicing, the glass carrier remains part of the package and does not have to be removed.

Most other products will need temporary wafer support after thinning. Back-grinding tapes lend some stability to the wafer, but become difficult to use when vacuum or high-temperature processes are needed, or if wafers become ultra thin. Alternatives are temporary bonding of wafer and support carrier, or the use of electrostatic carriers. Whatever option the industry goes for, equipment suppliers will strive to modify their process equipment as little as possible to adapt them to thin wafer handling. Therefore, fully automated process lines will not handle unsupported thin wafers, especially for technologies involving a large number of process steps. Yield considerations simply call for a carrier solution.

After all this discussion about 3D packaging, it should not be overlooked that there still are plenty of 2D innovations. Fan-out WLP, for example, the embedded wafer-level BGA (eWLB) from Infineon, is expected to overcome interconnect density limitations of PC boards and reduce the need for bump interconnects. With fan-out WLPs, an artificial reconfigured wafer is realized by populating a carrier wafer with sets of singulated die. Gaps are then filled with a suitable material and an RDL layer is added. The RDL layer takes over the role of a high-density board by interconnecting the dice to create complex modules. Moreover, by integrating passives into the fan-out WLP, an ultra-high package density can be achieved. Naturally, this technology offers its specific challenges to lithography tools such as warped wafer handling, run-out caused by the tolerances of die placement, and topography variations of the reconfigured wafer.

In conclusion, advanced packaging continues to offer equipment suppliers plenty of opportunities to drive advanced equipment performance. At least from the equipment point of view, there is a lot of synergy between 3D packaging and MEMS. I am therefore very confident that the economy-of-scale will work out, and that the advanced packaging market actually has never been more attractive than it is today.

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DIETRICH TÖNNIES, Ph.D., global business manager, mask aligners, may be contacted at SUSS MicroTec, AG Schleissheimer Strasse 90, Garching, Germany, D-85749; +49 08 932007149/E-mail: