Flash Memory for Stacked PoP Technology Issues and Test Challenges
BY KENNETH SEAH, BERTRAND WONG, GOH SWEE HENG, and TAN CHOON LENG, STATS ChipPAC Ltd.
Flash memory has become a fundamental building block in modern electronic systems. Package-on-package (PoP) stacking achieves the smallest package body size, mix-and-match logic with multiple memories, and flexibility of assembly. However, the flash memory integration in PoP introduces system reliability and test challenges at both the individual and stacked packaged levels.
With the rapidly growing semiconductor market, there is a demand placed on mobile appliances such as communications, computing, and entertainment. Electronic equipment manufacturers have increasingly required cost-effective non-volatile memory (NVM) solutions to maintain data or software codes. Low-cost NAND flash memory devices have filled this need and have established a vital position in the semiconductor industry. As a critical component in market-leading mobile products, including cellular phones, handheld computers and digital cameras, flash memories are one of the fastest growing market segments (Figure 1).
Figure 1. Revenue of memory shipped.
Flash memory is the ideal candidate for integrated memory implementation because its content can be changed and updated in the field, providing flexibility required by modern systems. Therefore, the best approach is to use 3D packaging assembly technology, such as PoP configuration. A PoP stack can consist of a bottom package containing a high-performance logic device and a top package typically containing high-capacity or multiple memory devices. It provides a cost-effective and flexible solution, and has become an important feature for system manufacturers since they are able to select the top and bottom components from various sources.
However, the integration of flash memory in PoP introduces critical issues and challenges to systems, technology, and test.
NAND Flash Memory
NAND flash is gaining popularity in consumer products because it’s cheaper than conventional NOR flash. Effective evaluation of cost and reliability is crucial. For an effective estimation, the manufacturer should accurately evaluate the possibilities of flash memory offered in the markets and its capability to integrate on other packages.
Reliability is another critical constraint for non-volatile memory (NVM) in general, and even more for flash memory PoP. Integration with high-performance logic severely threatens flash memory reliability because of the compatibility between the memory and the logic controller. In particular, there are some specific technology issues to be addressed for a reliable PoP integration.
PoP technology vertically combines discrete logic and memory BGA packages. Two or more packages are stacked on top of one another with standard interface-to-route signals between them (Figure 2). The industry is focusing on this cross-section figure as the key technology.
Figure 2. Typical PoP structure.
PoP stacking offers benefits such as reduced footprint on the PCB. Another important benefit is the minimized track and wire length between, for example, a controller and a memory. This results in better electrical performance of the devices. Furthermore, PoP provides great flexibility when selecting a memory device, chaining memory density, and sourcing the package supplier.
Figure 3. An example of package warpage.
Increased market demand has determined the growth of stacked PoP technology. Since the top and bottom packages are usually from different suppliers, the assembly process has to be carefully selected to optimize and enable high yield because both the top and bottom packages experience warpage, which varies in reflow process (Figure 3). Note how some joints press down and are deformed, while another is being opened and collapses due to package warpage.
In a typical asymmetrical package, warpage can either be concave (smiling face) or convex (crying face). Warpage is the result of residual stress induced by non-uniform package shrinkage. Depending on the degree of polymerization during molding, application of external clamping force during the post-mold cure process can help to attenuate the effect of internal residual stress. The amount of package warpage changes with varying temperature, such as during reflow where the temperature typically reaches 260??C. This is due to the difference in expansion between the various components in the package.
Various techniques have been developed to counter this effect. The addition of smaller solder balls on the top pad of the bottom package helps absorb the effect of package warpage, while keeping the total volume of solder paste used to a minimum. While the selection of flux or paste used during final PoP assembly also contributed to a better joint formation, countering the gap left due to package warpage, the addition of higher melting point metal flakes in the paste used facilitates bridging and filling of the gap left behind during reflow.
With the advancement in technology, the increasing demand of stacking flash memories with other logic devices has made testing a challenging task in three major areas: cost, test platform capabilities, and test strategies.
Cost of test is perhaps the single greatest challenge among the sources of cost for flash manufacturers. Increasing NVM device complexity and falling chip prices is driving manufacturers to focus on cost of test to prevent further erosion of the profit margin. Flash manufacturers reduce the cost of test by developing test methodologies that reduce test time, increasing parallelism and throughput, as well as enhance flexibility and scalability of test equipments.
Test Platform Capabilities
Advances in flash technology levy new requirements on test platform capabilities. For example, higher device speed requires a test platform with higher frequency and greater bit-rate capabilities. Thus, the increasing memory speed requirement could exceed the test system performance.
3D packaging requires a flexible test platform that can test stacked memory modules and logic device with a single insertion. Pattern flexibility of the test system is essential, and switching between algorithmic pattern generation and vectors ”on-the-fly“ within a single pattern is also required. These capabilities go beyond the scope of many traditional test platforms.
With the challenges mentioned, it is difficult to find a dedicated memory or logic test system suited to the demands for single-insertion test on integrated/stacking devices. Many manufacturers still apply the multiple insertions of different test systems to test individual components.
Requirements and Process Flow
Low cost-of-ownership is still the most critical for flash manufacturers looking to optimize resources and reduce their cost structure. Therefore, an effective solution to evolve flash test requirements with low cost is difficult to establish. Nevertheless, a reasonable summary of general platforms requirements can be given and a real case test process flow of a stacked NAND flash memory with high-speed logic controller exists.
General Platforms Requirements
To support increasing test complexity of flash devices, an effective solution needs to have a good combination of flexible architecture, high-performance instrumentation, and cost. Such a solution must address the existing demand for highly efficient test and must be scalable to match a company’s fluctuating production test needs.
A Practical Test Process Flow
Flash memory manufacturers face significant pressure to reduce costs despite advancing device complexity. Manufacturers expect to find a test platform solution that delivers more capabilities with minimum cost at both capital cost of acquisition and recurring cost of ownership. Therefore, a practical test solution for PoP flash devices must address the requirements of both the cost-effective production solution and the versatile engineering system. Multiple insertions test is still favored for PoP integration since this enables the reuse of existing test equipments.
Figure 4. Test process flow.
An example of practical test flow for PoP is shown in Figure 4. In this example two packages are stacked. The top package is a multi-chip package that stacks four of the NAND flash memory. The bottom package is a single chip package and known as a high-speed logic controller. There are land pads on the front side of the bottom package. These land pads are used for electrical communication between the top and bottom packages by mounting the top package on them. A beneficial feature of this package solution is that each individual package can be tested for full functionality before it is stacked. In other words, the known good package can be selectively integrated for final assembly.
The stacking of flash memory with advanced high-performance logic is still the most popular path to integrate systems requiring non-volatile memories. A real-case test process flow offers semiconductor manufacturers with the test capability, performance, and flexibility needed to reduce the cost-of-test for integrated flash PoP devices.
KENNETH SEAH, deputy director, test development and product engineering; BERTRAND WONG, quality assurance. GOH SWEE HENG, test development engineer, test development and product engineering; and TAN CHOON LENG, senior test development engineer, est development and product engineering; may be contacted at STATS ChipPAC Ltd. 10 Ang Mo Kio Street 65, #05-17/20 Techpoint, Singapore 569059, 65/6824-7777; Kenneth.email@example.com; firstname.lastname@example.org; email@example.com.