UBM: Creating the Critical Interface
A variety of bumping technologies are in use today. Electroplating is used for fine-pitch (<250 μm) solder bumping, while robotic ball placement is used for larger pitch, lower (<100) I/O applications. Image sensors for cell phones use a through-silicon-via (TSV) to connect a solder bump on the back side of the chip to the metal pad on the die surface. 3D chip stacking use micro-bumps deposited by electroplating.
All these bumping technologies require under bump metallization (UBM) to meet package reliability requirements. UBM provides the critical interface between the metal pad of the integrated circuit (or the Cu or Al trace) and the solder (or gold) bump. To prevent direct reaction between solder or gold and the chip metallization, a diffusion barrier of Ti or TiW is deposited by sputtering on top of the IC metallization (Al or Cu). It also acts as an adhesion layer, for the wetting layer deposited on top of it in the case of solder bumping, and for the Au seed layer for electroplating of gold, in the case of gold bumping. TiW is used for gold bumping applications due to its superior barrier properties. In the case of solder bumping, Ti or TiW can be used, as the diffusion barrier is provided by the wetting layer (Ni or Cu) deposited on top of the adhesion/barrier layer (Ti or TiW).
Figure 1. Flip chip interconnect scaling. (Courtesy of IMEC)
The solder wetting layer is a single layer or combination of Cu, Ni, (or NiV) and Au. A thin gold layer (100 – 200 nm) is deposited on top of the Ni layer to prevent oxidation and improve wettability. This gold layer is not required if the solder is deposited by electroplating directly on top of the Ni. In gold bumping, the gold seed layer for electroplating of the gold bump is sputtered on top of the TiW layer. In the case of solder bumping, the wetting layer deposited on top of the Ti or TiW layer can be deposited entirely by sputtering or by a combination of sputtering and electroplating. Sputtering is the preferred method for layers that are a few thousand Angstroms thick, and electroplating is preferred for thicker layers. The required UBM thickness depends on the solder/UBM combination and the reliability requirements of the device. The UBM (2 – 5 μm of Cu and or Ni) and the solder can both be deposited by electroplating using the same resist mask. Electroplating offers the advantage of depositing the UBM layer(s) only in the patterned area under the bump, simplifying the subsequent UBM etch processes.
During solder reflow — and subsequent lifetime of device — an intermetallic compound (IMC) is formed between the Sn in the solder material and the wetting layer. This acts as a diffusion barrier between the solder and the chip metallization. Consumption of the solder to form an IMC is advantageous from an adhesion point of view, but results in a brittle compound, which reduces the ductile fraction of the solder joint required to take up the deformation due to thermal mismatch with the substrate.
Consumption of the UBM depends on the solder type and the UBM material. Lead-free solders rich in Sn consume more UBM than SnPb solders. Ni has a much slower reaction with Sn than Cu during solder reflow. Adhesion is lost if the solder or IMC reach the underlying non-wettable layers (Ti or TiW).
The IMC thickness is independent of the bump height and therefore the relative amount of IMC to un-reacted solder is much larger for smaller solder bumps. In fine-pitch (20 μm) solder bumping, the entire solder volume may be transformed into IMC. These micro-bumps made up entirely of IMC (some un-reacted UBM is required to ensure good adhesion) have a melting point several hundred degrees higher than the temperature required to form the IMC. This offers enhanced thermal stability and resistance to electromigration; smaller solder bumps have a higher risk of electromigration due to larger current density. However, the brittle nature of the IMC limits the use of these micro-bumps to connections with small CTE mismatch, such as used in 3D chip stacking.
These micro bumps have stringent thickness uniformity requirements as there is no compliant volume to accommodate uniformity mismatches. As we transition to fine pitch geometries for 3D chip stacking, bump dimensions will become similar to those of the UBM.
KATHY O’DONNELL, Ph.D., director, business development, may be contacted at NEXX Systems, 5 Suburban Park Dr. Billerica, MA 01821; 978/932-2060; Kathyemail@example.com