Bonding Solutions for 3D Integration
BY SHARI FARRENS, Ph.D., AND SUMANT SOOD, SUSS MicroTec
Throughout the past several years, various bonding methods for use in 3D integration have been undergoing evaluation. Industry buzzwords include through silicon vias (TSVs), via first, via last, integrated solutions, and so forth. The encouraging news is that several products are starting to emerge from R&D and head for manufacturing. Currently, three technologies lead the way for wafer-to-wafer bonding for production applications. These include silicon direct or fusion bonding, adhesive bonding, and copper diffusion bonding. Each method has distinct limits and requirements for successful, high-yield bonds. Figure 1 highlights the diversity in approaches and range of interest in 3D processing.1 As indicated, there are some hybrid approaches as well, and companies continue R&D in this high-potential technology.
Figure 1. 3D wafer level bonding methods indicating major players, developers, and temperature regimes.
The requirements for 3D integration can be summed up by the statement, “alignment, alignment, and (did we mention) alignment”. The fundamental key of vertical integration is the ability to connect devices electrically across thin vertical distances rather than the lengthy lateral routing paths used in conventional 2D architectures. Thus the size and pitch of interconnects determine the requirements for alignment accuracy. Designs currently headed into production ramps for 2008 target 1-2 μm overlay registry with roadmaps heading toward deep submicron levels by 2010. A key factor that affects alignment accuracy is the temperature of the bonding process. Therefore, there is an inherent difference between the three leading methods. Superimposed on the thermal expansion issues are the differences in alignment methods, quality and type of alignment keys, and mechanical contributions of the equipment set.
Copper-to-copper (Cu-Cu) diffusion bonding is done by aligning two wafers face-to-face and bringing them into contact under vacuum or reducing environments. The wafers are then pressed together with 20-40KN of force and heated to 400-425??C for roughly 30 minutes. The manufacturing challenges that have been addressed involve tight thermal uniformity control across the wafer and uniform heating from both sides of the wafer stack. This is important to control the thermal expansion rates of the upper and lower wafer with respect to one another so that alignment accuracy can be maintained. Champions of this approach include Tezzaron, Intel, and MIT. Figure 2 is a cross section of a copper interconnect bond that shows, with proper surface preparation, that the bond interface is indistinguishable from the bulk material.
Figure 2. SEM image of a bonded copper interface for 3D interconnect. Due to formic acid vapor surface preparation and proper bonding conditions, no interface is visible and electrical conductivity is excellent.
In most applications, bonds are not made with blanket layers of copper. In other words, instead of wafers that have 100% coverage of surface copper, a more typical structure involves copper vias that have undergone chemical mechanical polishing (CMP) to be planar with the surrounding dielectric layer. The dielectric materials are deposited oxides that provide electrical isolation of the copper vias. The vias will represent less than 30% of the total exposed area. In this case, when the wafers are bonded, copper areas are in contact with other copper areas and oxide-to-oxide area contact constitutes the bulk of the wafer interface. During the annealing process, the oxide-to-oxide areas will develop covalent bonds simultaneously to the metallic bonds being formed through diffusion processes across the vias. To increase the yield in this hybrid approach, it is useful to also consider plasma activation of the surface to increase the covalent bond formation between the oxide layers. Much of this work has been pioneered by Ziptronix.2
A similar bond methodology is the silicon-direct bonding method. In this case, the bond interface is 100% oxide. The metal layers are below the surface and will be contacted later by deep reactive ion etching (DRIE) and via formation after the bonding. The typical process flow involves preparation of smooth flat oxide surfaces. Alignment and bonding are done in the same tool, called the bond aligner. Because the oxide surface can be made hydrophilic through a variety of chemical or plasma treatments, the substrates will bond spontaneously through weak van der Waals forces in the aligner. Alignment is done with the wafer held in close proximity (typical a few 10s of microns) and after the alignment is complete, the spacers are removed and contact is initiated at room temperature. Although the van der Waals forces are weak, they are sufficient to hold the wafer in precise alignment while the wafers are transferred to a batch annealing process. This process eliminates the thermal expansion shifts between wafers due to coefficient of thermal expansion (CTE) mismatch. The limitations to silicon direct bonding is the inability to achieve reproducible and high quality surface smoothness necessary for spontaneous bond formation. The requirement for silicon direct bonding is <1 nm of RMS surface roughness.
Benzocyclobutene (BCB) bonding has been very successful as a demonstrator for 3D IC integration using adhesive techniques. The completed wafers are coated with a few microns of BCB by uniform spin coating. The substrates are aligned and then bonded in a thermal compression bonder similar to the copper diffusion process described above. Because the bond temperature is 300-320??C and the bond time is much shorter, the throughput of the overall process increases, and there is less potential for thermal-expansion-induced misalignment or run-out relative to the Cu-Cu diffusion method.
Clearly there are two critical nodes during the production of 3D integrated devices; alignment and bonding. Alignment methods involve the visualization of alignment keys from each of the substrates and the mechanical positioning of the wafers to bring these keys into registry. The alignment methods include backside alignment (BSA), inter-substrate alignment, or infrared alignment (IR). Manufacturers of 3D bonding equipment are able to provide production tools capable of 1.0 to 1.5-μm alignment accuracy. What will be needed for production and future designs will decrease dramatically over the next few years as production ramps begin.
It appears that the alignment technology that will move forward will be methods that allow the visualization of front side targets in real time. Only two of the previously listed methods allow for this type of alignment: IR and inter-substrate imaging. In IR imaging, the light is transmitted through the wafer to a CCD camera. Attenuation of the signal in the silicon and interference from opaque metal layers limit the viability of this method to two wafer stacks with low-density metallization. Thus, inter-substrate cameras offer a huge advantage. Alignment to live images ensures that during the entire alignment process, both alignment keys are observed in real time. This allows for detection of minute alignment shifts during all mechanical movements and the correction of errors during movement.
Wafer-to-wafer vs. Die-to-wafer
The primary advantage of wafer-to-wafer level 3D integration is the throughput advantage of interconnecting all the die in one step. However, this requires that both wafers are high yielding and that die sizes and wafer diameters are the same geometry and diameter. Thus not all 3D applications will use wafer-to-wafer level bonding. Many of the initial products going to market will actually start with die-to-wafer stacking technology. The alignment requirements for die-to-wafer technology are slightly less stringent than the goals of the wafer-to-wafer approach. Die-to-wafer bonding generally requires 2-3 μm of alignment at each die location with near-term goals of improving the placement accuracy to 1 μm. The current limitation to volume production is placement speed. To become a viable manufacturing method, placement speeds need to approach 1000 die/hr or more. This is not currently possible with the desired alignment accuracy needed and is the focus of equipment design throughout the industry.
Table 1. Roadmap for 200 and 300 mm 3D wafer-to-wafer level integration. (Alignment is in microns, 3 sigma.)
Hybrid approaches are also being considered in which a high-speed placement tool is used to locate die on 300-mm wafers using temporary adhesives or tacking methods. Then the populated die-on-wafer stack is placed in a modified wafer-level bonder for the final bond which takes moderate temperatures and longer reaction times that would impair the throughput of the traditional die bonder.
Table 1 is a near term roadmap for wafer-to-wafer level bonding activities. These goals will be met with equipment sets specifically designed to address the needs of the 3D market. These tools have enhanced alignment features, revolutionary bonder designs and specific fixturing to enable submicron 3D integration to become reality.
- Yole “3D IC Report Feb. 2007”, 45 rue Sainte Geneviève, F-69006 Lyon, France, www.yole.fr.
- Paul Enquist, “Direct Bond Interconnect (DBI™) -Technology for Scaleable 3D SoCs”, RTI Conference Proceedings on Semiconductor Integration and Packaging Accessing Technological Developments, Applications, and Key Enablers, 31 OCT – 2 NOV 2006, Marriot San Francisco Airport Hotel, Burlingame, California.
SHARI FARRENS, Ph.D. chief scientist, wafer bonder division, AND SUMANT SOOD, application engineer, may be contacted at SUSS MicroTec, 228 Suss Drive, Waterbury Center, VT 05676; 802/244 5181; firstname.lastname@example.org.